Gateway Model Routing with Slits on Wires
Granted: May 22, 2014
Application Number:
20140143747
A computer-implemented method for routing at least one conductor includes generating the at least one conductor within a bounded region on a planar surface in accordance with a template, and placing at least one slit in the conductor when the conductor overlaps a specified region of the bounded region in accordance with a specified pattern.
Automated Circuit Design
Granted: May 22, 2014
Application Number:
20140143743
A method implemented on a data processing system for circuit synthesis is discussed. In one embodiment, the method comprises determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources, and splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads.
Packet Switch Based Logic Replication
Granted: May 15, 2014
Application Number:
20140137056
A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source…
Method for Ranking Fault-Test Pairs Based on Waveform Statistics in a Mutation-Based Test Program Evaluation System
Granted: May 15, 2014
Application Number:
20140136900
Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a…
ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE
Granted: April 24, 2014
Application Number:
20140115556
Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account…
COMPRESSED INSTRUCTION CODE STORAGE
Granted: April 24, 2014
Application Number:
20140115304
Computer implemented techniques are disclosed for identification of repeated binary strings and for storing those binary strings in order to compress code. The binary strings can be longer instructions, data, or addresses. A table of binary strings is generated based on repeated occurrences, and a reference index is provided for accessing specific entries within the table. An opcode uses a shorter string as an index through which to access the table. The longer string is executed when…
MODELING AND CORRECTING SHORT-RANGE AND LONG-RANGE EFFECTS IN E-BEAM LITHOGRAPHY
Granted: April 24, 2014
Application Number:
20140114634
Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected…
ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS
Granted: April 17, 2014
Application Number:
20140109027
Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
Generation of Instruction Set from Architecture Description
Granted: April 17, 2014
Application Number:
20140109040
Generating an instruction set for an architecture. A hierarchical description of an architecture is accessed. Groups in the hierarchical description that can be pre-encoded without increasing final width of said instruction set are pre-encoded. The hierarchical description is permutated into a plurality of variations. Each variation comprises a leaf-group and one or more sub-graphs to be encoded. For each said variation, the leaf-group and the one or more sub-graphs are encoded to…
Timing Closure Methodology Including Placement with Initial Delay Values
Granted: April 17, 2014
Application Number:
20140109034
An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based…
Concurrent Host Operation And Device Debug Operation WIth Single Port Extensible Host Interface (XHCI) Host Controller
Granted: April 17, 2014
Application Number:
20140108870
An improved USB host controller and method supports concurrent host and device debug operations with only one usable USB port. The described embodiments save silicon cost and avoid additional connectors, which are undesirable in ever-smaller devices.
AUTOMATIC GENERATION OF INSTRUCTION-SET DOCUMENTATION
Granted: April 10, 2014
Application Number:
20140101638
A method and system for the automatic generation of user guides. Specifically, the method of the present invention includes accessing an abstract processor model of a processor, wherein said abstract processor model is represented using a hierarchical architecture description language (ADL). The abstract processor model includes a plurality of instructions arranged in a hierarchical structure. An internal representation of the abstract processor model is generated by flattening the…
AUGMENTED POWER-AWARE DECOMPRESSOR
Granted: April 3, 2014
Application Number:
20140095101
Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester.
MITIGATING CROSS-DOMAIN TRANSMISSION OF ELECTROSTATIC DISCHARGE (ESD) EVENTS
Granted: April 3, 2014
Application Number:
20140092507
An electrostatic discharge (ESD) device is implemented within a power domain to mitigate imparting ESD induced voltages on other power domains for reducing integrated circuit (IC) failures. A first power domain includes an interface with a first terminal where an ESD event is received. The interface includes a second terminal coupled to a component within a second power domain. The ESD device is disposed between the first terminal and second terminal to intercept the ESD event. In one…
AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS
Granted: March 27, 2014
Application Number:
20140089868
A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations…
ARCHITECTURAL PHYSICAL SYNTHESIS
Granted: March 20, 2014
Application Number:
20140082579
Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.
Method of Fast Analog Layout Migration
Granted: March 13, 2014
Application Number:
20140075402
A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
Method and Apparatus for Process Window Modeling
Granted: March 13, 2014
Application Number:
20140075398
A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the…
LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS
Granted: March 6, 2014
Application Number:
20140065821
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
INFORMATION THEORETIC SUBGRAPH CACHING
Granted: March 6, 2014
Application Number:
20140068533
Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be…
