DETERMINING OPTIMAL GATE SIZES BY USING A NUMERICAL SOLVER
Granted: January 30, 2014
Application Number:
20140033162
Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the…
METHOD FOR TESTING A COMPUTER PROGRAM
Granted: January 16, 2014
Application Number:
20140019925
A method for testing a circuit specification after changing a first version of the circuit specification into a second version of the circuit specification due to a revision of the circuit specification includes receiving a first set of mutations that can be or have been inserted into the first version of the circuit specification and a second set of mutations that can be inserted into the second version of the circuit specification computer program. Changed and unchanged mutations are…
SELF-ALIGNED VIA INTERCONNECT USING RELAXED PATTERNING EXPOSURE
Granted: January 16, 2014
Application Number:
20140015135
Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended…
HIERARCHICAL POWER MAP FOR LOW POWER DESIGN
Granted: January 9, 2014
Application Number:
20140013293
Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set…
ESTIMATING OPTIMAL GATE SIZES BY USING NUMERICAL DELAY MODELS
Granted: January 2, 2014
Application Number:
20140007037
Systems and techniques are described for estimating optimal gate sizes in a circuit design using numerical delay models of cells and cell types in a technology library. Gate sizes are optimized in the circuit design in a reverse-levelized processing order. Gates that are at the same level in the reverse-levelized processing order, and whose inputs are electrically connected to the same driver output are optimized together. A closed-form expression is used to determine the optimized size…
SRAM LAYOUTS
Granted: January 2, 2014
Application Number:
20140003133
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are…
Generation of Memory Structural Model Based on Memory Layout
Granted: December 26, 2013
Application Number:
20130346056
A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy…
Simulation with Dynamic Run-Time Accuracy Adjustment
Granted: December 26, 2013
Application Number:
20130346046
Systems and methods for simulation with dynamic run-time accuracy adjustment. In one embodiment, a first portion of a sequence of software instruction is simulated by a first simulation model, during a simulation. During the same simulation, a second portion of the sequence is simulated by a second simulation model. State information may be transferred from the first simulation model to the second simulation model. A change from simulating the first portion of a sequence of software…
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE
Granted: December 19, 2013
Application Number:
20130334613
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a…
CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES
Granted: December 19, 2013
Application Number:
20130339915
A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the…
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH
Granted: December 19, 2013
Application Number:
20130334610
A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer…
FLOATING GATE NON-VOLATILE MEMORY BIT CELL
Granted: December 12, 2013
Application Number:
20130328117
A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes…
Method and Device For Reconstructing Scan Chains Based On Bidirectional Preference Selection in Physical Design
Granted: December 5, 2013
Application Number:
20130326462
Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device,…
INCREMENTAL ELMORE DELAY CALCULATION
Granted: December 5, 2013
Application Number:
20130326449
Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the…
DEBUG IN A MULTICORE ARCHITECTURE
Granted: December 5, 2013
Application Number:
20130326283
A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative…
DEBUG IN A MULTICORE ARCHITECTURE
Granted: December 5, 2013
Application Number:
20130326282
A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative…
EXCLUDING LIBRARY CELLS FOR DELAY OPTIMIZATION IN NUMERICAL SYNTHESIS
Granted: November 28, 2013
Application Number:
20130318488
Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater…
PREVENTING ELECTROSTATIC DISCHARGE (ESD) FAILURES ACROSS VOLTAGE DOMAINS
Granted: November 28, 2013
Application Number:
20130314824
An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating…
METHOD FOR DETECTING AND DEBUGGING DESIGN ERRORS IN LOW POWER IC DESIGN
Granted: November 14, 2013
Application Number:
20130305207
A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly…
QUASI-DYNAMIC SCHEDULING AND DYNAMIC SCHEDULING FOR EFFICIENT PARALLEL SIMULATION
Granted: November 7, 2013
Application Number:
20130297279
An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic…
