RETIMING A DESIGN FOR EFFICIENT PARALLEL SIMULATION
Granted: November 7, 2013
Application Number:
20130297278
An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that…
SELECTIVE EXECUTION FOR PARTITIONED PARALLEL SIMULATIONS
Granted: October 31, 2013
Application Number:
20130290919
Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a…
GROUND OFFSET MONITOR AND COMPENSATOR
Granted: October 31, 2013
Application Number:
20130285641
Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known…
NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL AND/OR A TECHNOLOGY LIBRARY CELL TYPE
Granted: October 24, 2013
Application Number:
20130283222
Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized…
OPTIMIZING LOGIC SYNTHESIS FOR ENVIRONMENTAL INSENSITIVITY
Granted: October 3, 2013
Application Number:
20130263069
Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in…
SYSTEM AND METHODS FOR HANDLING VERIFICATION ERRORS
Granted: September 26, 2013
Application Number:
20130254727
Systems, apparatus and methods for handling verification violations are disclosed. In one aspect, a method stores a list of fix information in addition to geometric shapes for each layer during verification, such as design rule checking For each primitive operation step performed during verification, two tasks are performed. First, if the primitive operation is a dimensional checking operation (i.e., width, spacing or enclosure), then for each violation, the first task creates fix…
APPROXIMATE FUNCTIONAL MATCHING IN ELECTRONIC SYSTEMS
Granted: September 26, 2013
Application Number:
20130254430
Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.
Electronic Circuit Simulation Method With Adaptive Iteration
Granted: September 19, 2013
Application Number:
20130246015
In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the…
Circuit Design and Retiming
Granted: September 12, 2013
Application Number:
20130239081
A method and apparatus to design a circuit is described. In on embodiment, the method comprises selecting a target clock for a design of the circuit, and determining a plurality of latencies for a portion of the circuit. The method further comprises determining a representation of a data flow graph for the portion of the circuit, the data flow graph having a first node connected with a second node by a number of extra delays determined based on the target clock and the plurality of…
ATPG AND COMPRESSION BY USING MAJORITY GATES
Granted: September 5, 2013
Application Number:
20130232459
A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.
Increasing PRPG-Based Compression By Delayed Justification
Granted: September 5, 2013
Application Number:
20130232458
An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines,…
METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING
Granted: August 29, 2013
Application Number:
20130227511
In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global…
PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS
Granted: August 29, 2013
Application Number:
20130227509
A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on…
Recursive Hierarchical Static Timing Analysis
Granted: August 29, 2013
Application Number:
20130227507
A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the…
DATA FLOW ANALYZER
Granted: August 29, 2013
Application Number:
20130227503
A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The…
STATIC READ ONLY MEMORY DEVICE WHICH CONSUMES LOW STAND-BY LEAKAGE CURRENT
Granted: August 22, 2013
Application Number:
20130219200
An electronic device comprises a semiconductor memory cell having a bistable bit storage circuit having first and second power contact points. A first switch is coupled to the first power contact point to receive a first voltage. A second switch coupled to the second power contact point to receive a second voltage. Circuitry is provided for turning off the first and second switches to decouple the respective first and second voltages from the respective first and second power contact…
COORDINATING AND CONTROLLING DEBUGGERS IN A SIMULATION ENVIRONMENT
Granted: August 15, 2013
Application Number:
20130212566
A simulation environment, in one embodiment, includes a debugger server, one or more debuggers, and one or more debugger adapters. Each debugger adapter couples a corresponding debugger to the debugger server. The debugger server coordinates the run mode of the debugger adapters. Each debugger adapter controls the run mode of its corresponding debugger.
STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN
Granted: August 8, 2013
Application Number:
20130200945
Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal…
Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor
Granted: August 1, 2013
Application Number:
20130193498
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately…
Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor
Granted: August 1, 2013
Application Number:
20130193501
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately…
