SCALABLE PATTERN MATCHING BETWEEN A PATTERN CLIP AND A PATTERN LIBRARY
Granted: August 1, 2013
Application Number:
20130195368
A two-level matching technique is described. A system can generate a set of index patterns based on a set of library patterns in a pattern library. The pattern library can include patterns that are expected to have problems during manufacturing. Next, the system can use a fast matching process to check if a first-level pattern clip potentially matches one or more index patterns from the set of index patterns. If so, the system can use a detailed matching process to match a second-level…
SIMULATION CONTROL TECHNIQUES
Granted: July 25, 2013
Application Number:
20130191346
Simulation control techniques include shutting down peer processes and user code modules, storing an image of a simulation as a checkpoint after the peer processes and user code modules are shutdown, and re-starting user code modules and peer processes after storing an image of the simulation. The resulting checkpoint and processes can be used for restoring from a checkpoint or restarting a new simulation environments having peer processes such as debuggers coupled to the simulation.
PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES WITH IMPROVED TRANSFER FUNCTION
Granted: July 25, 2013
Application Number:
20130187802
A connection scheme is used to selectively connect a dither capacitor included in a calibrated stage of a pipeline analog-to-digital converter (ADC) in a way that reduces the output voltage swing of the stage. A first terminal of the dither capacitor is coupled to an input of the amplifier. A second terminal of the dither capacitor is coupled to either a first or second reference voltage dependent on a bit value in a Pseudo-Random Binary Sequence (PRBS) if a voltage received by the stage…
GAIN AND DITHER CAPACITOR CALIBRATION IN PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES
Granted: July 25, 2013
Application Number:
20130187801
A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that…
Dynamic Biasing of an Amplifier Using Capacitive Driving of Internal Bias Voltages
Granted: July 25, 2013
Application Number:
20130187629
A system and a method are disclosed for using driving capacitors to dynamically bias an amplifier in a stage of a pipeline analog-to-digital converter (ADC). The drain of the amplifier is connected to a sink transistor, and the driving capacitors are used to raise or lower the voltage at the gate of the sink transistor. The driving capacitors can be used in this manner to rapidly power the amplifier on and off to save power and/or to selectively boost the drain current of the amplifier…
MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION
Granted: July 4, 2013
Application Number:
20130174115
An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is…
DETERMINING LARGE-SCALE FINITE STATE MACHINES USING CONSTRAINT RELAXATION
Granted: July 4, 2013
Application Number:
20130173245
A computer-implemented method of finite state machine using constraint relaxation. A first expression having a plurality of variables is accessed. A second expression is accessed that describes a constraint with respect to a first variable of the plurality of variables. At least one of the variables from the second expression is eliminated to create a third expression with the constraint relaxed. The third expression is applied to the first expression to determine a finite state machine…
Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers
Granted: July 4, 2013
Application Number:
20130171548
A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions…
HIGH-VOLTAGE SWITCH USING THREE FETS
Granted: June 27, 2013
Application Number:
20130162326
Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that…
REDUCTION OF SPATIAL PREDICTORS IN VIDEO COMPRESSION
Granted: June 27, 2013
Application Number:
20130163671
A system and a method are disclosed for encoding and decoding a video frame using spatial prediction. The video frame is separated into a plurality of image blocks, and a plurality of spatial predictors is created for an image block using methods well-known in the art. The set of predictors is reduced to a set containing fewer spatial predictors before continuing the coding process for the block. The reduction of spatial predictors involves comparing a plurality of spatial predictors and…
EQUATION BASED TRANSIENT CIRCUIT OPTIMIZATION
Granted: June 20, 2013
Application Number:
20130159958
Circuit simulation can be performed on digital, analog, and mixed signal types of circuitry. Phases of operation are identified for a circuit and transient behavior is analyzed. Multiple time points are identified and the circuit is replicated for those time points with evaluation of the circuitry performed at those various time points. Simultaneous optimization is performed across the time points. Transistors and other devices can have their lengths, widths, and number of fingers…
HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE
Granted: June 20, 2013
Application Number:
20130159949
Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be…
METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN
Granted: June 13, 2013
Application Number:
20130152031
A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating…
EFFICIENT TIMING CALCULATIONS IN NUMERICAL SEQUENTIAL CELL SIZING AND INCREMENTAL SLACK MARGIN PROPAGATION
Granted: June 6, 2013
Application Number:
20130145339
Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source…
MODELING TRANSITION EFFECTS FOR CIRCUIT OPTIMIZATION
Granted: June 6, 2013
Application Number:
20130145338
Systems and techniques are described for determining a transition-effect model for a timing arc of a library cell. A transition-effect model can be determined for each library cell that is used during an optimization process. The transition-effect models enable an optimization system to estimate the impact of a change in the transition at an output of a driver gate on the delays of downstream gates without requiring to propagate the change in the transition to the downstream gates. Once…
DELTA-SLACK PROPAGATION FOR CIRCUIT OPTIMIZATION
Granted: June 6, 2013
Application Number:
20130145337
Systems and techniques for optimizing a circuit design are described. When a selected gate is transformed during optimization, it causes a slack value at a pin of the transformed gate to change. The change in the slack value, called the delta-slack, is then propagated through a transitive fanin cone and a transitive fanout cone of the transformed gate to compute the new slack values at all the affected pins of the design. Some embodiments update slack values without propagating arrival…
PROGRESSIVE CIRCUIT EVALUATION FOR CIRCUIT OPTIMIZATION
Granted: June 6, 2013
Application Number:
20130145336
Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design.…
SEQUENTIAL SIZING IN PHYSICAL SYNTHESIS
Granted: June 6, 2013
Application Number:
20130145331
Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing…
Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme
Granted: June 6, 2013
Application Number:
20130145119
A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling,…
RFID TAG HAVING NON-VOLATILE MEMORY DEVICE HAVING FLOATING-GATE FETS WITH DIFFERENT SOURCE-GATE AND DRAIN-GATE BORDER LENGTHS
Granted: May 30, 2013
Application Number:
20130135933
Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be…
