HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE
Granted: May 23, 2013
Application Number:
20130132919
Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be…
Electronic Device, System on Chip and Method for Monitoring a Data Flow
Granted: May 23, 2013
Application Number:
20130132564
An electronic device is provided which comprises a plurality of processing units (IP1-IP6), a network-based interconnect (N) coupled to the processing units (IP1-IP6) and at least one monitoring unit (P1, P2) for monitoring a data flow of at least one first communication path between the processing units (IP1-IP6) and for forwarding monitoring results at least temporarily via at least two separate communication paths (MC1, MC2).
MODELING MASK ERRORS USING AERIAL IMAGE SENSITIVITY
Granted: May 23, 2013
Application Number:
20130131857
One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent…
METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY
Granted: May 16, 2013
Application Number:
20130125075
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations…
ACCELERATING COVERAGE CONVERGENCE AND DEBUG USING SYMBOLIC PROPERTIES AND LOCAL MULTI-PATH ANALYSIS
Granted: May 9, 2013
Application Number:
20130117722
In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions,…
METHOD AND APPARATUS FOR TURNING CUSTOM PROTOTYPE BOARDS INTO CO-SIMULATION, CO-EMULATION SYSTEMS
Granted: May 9, 2013
Application Number:
20130117007
A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design.…
Method and apparatus for floating or applying voltage to a well of an integrated circuit
Granted: May 9, 2013
Application Number:
20130113547
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the…
RATE DISTORTION OPTIMIZATION IN IMAGE AND VIDEO ENCODING
Granted: April 11, 2013
Application Number:
20130089137
An offline quantization module is used to optimize a rate-distortion task. The offline quantization module calculates a quantization kernel for a range of computable block parameters and a range of rate-distortion slope values representing the rate and complexity of a coded video. A quantization kernel is utilized by an encoder application for content-adaptive quantization of transformed coefficients. The quantization kernel includes a block data model, a quality metric model, and an…
PARASITIC EXTRACTION FOR SEMICONDUCTORS
Granted: April 11, 2013
Application Number:
20130091480
Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.
VISUAL QUALITY MEASURE FOR REAL-TIME VIDEO PROCESSING
Granted: April 11, 2013
Application Number:
20130089150
A measure of visual quality of processed images relative to unprocessed images is generated in real-time. The measure of visual quality closely correlates with a human's actual perception of the processed image relative to the original image. The measure of visual quality is computed based on a measure of discrepancy (e.g., mean square errors) between the processed and unprocessed images and the variance of each image in the pixel domain or the transform domain may be determined. If the…
INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA
Granted: April 4, 2013
Application Number:
20130086535
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the…
EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION
Granted: April 4, 2013
Application Number:
20130085738
One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a…
MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES
Granted: March 28, 2013
Application Number:
20130080847
A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port,…
METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE
Granted: March 14, 2013
Application Number:
20130065380
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall…
METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES
Granted: February 21, 2013
Application Number:
20130047127
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
Methods and Apparatuses for Automated Circuit Design
Granted: February 14, 2013
Application Number:
20130042215
Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the…
Standard Cell Placement Technique For Double Patterning Technology
Granted: February 7, 2013
Application Number:
20130036397
A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed…
INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME
Granted: January 31, 2013
Application Number:
20130026607
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE WITH INTER-BLOCK INSULATOR
Granted: January 31, 2013
Application Number:
20130026571
A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the…
NVM Bitcell with a Replacement Control Gate and Additional Floating Gate
Granted: January 31, 2013
Application Number:
20130026553
Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.
