INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME
Granted: January 31, 2013
Application Number:
20130026607
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
SCALABLE LANGUAGE INFRASTRUCTURE FOR ELECTRONIC SYSTEM LEVEL TOOLS
Granted: January 24, 2013
Application Number:
20130024839
Systems and methods of scalable language infrastructure for electronic system level tools. In accordance with embodiments of the present invention, knowledge about types, functions and the like is encapsulated in a plurality of intelligent components called active component extension modules that are external to the infrastructure. The infrastructure implements a communication mechanism between the clients and these intelligent components, and acts as a common backbone. The…
DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY
Granted: January 17, 2013
Application Number:
20130019132
A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of…
TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY
Granted: January 17, 2013
Application Number:
20130019130
Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The…
HIGH-SPEED VOLTAGE-LEVEL CONVERTER USING CAPACITOR
Granted: January 17, 2013
Application Number:
20130015994
A voltage-level convertor including a switch and a capacitor which receives an input signal of a first voltage range and generates a level-converted signal of a second voltage range. The switch operates in a low voltage level, and hence, the switch can be implemented as a thin oxide device that responds quickly to the input signal. The capacitor is coupled between the switch and an output node. The capacitor is charged to a predetermined voltage. In response to receiving the output from…
SYNCHRONOUS SWITCHING IN HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER USING QUAD SYNCHRONIZING LATCH
Granted: January 17, 2013
Application Number:
20130015993
A synchronizing circuit compatible with a quad switching scheme in a digital-to-analog converter (DAC) to synchronize turning on or off of switches for steering current to a differential output. The synchronizing circuit receives signals from a decoder and synchronizes control signals to the switches by a clock signal. In one embodiment, the synchronizing circuit includes a predictor circuit and a latch circuit. The latch circuit may include four sets of cross-coupled inverters where a…
VOLTAGE REGULATION IN CHARGE PUMPS
Granted: January 17, 2013
Application Number:
20130015831
Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The…
Preconditioning For EDA Cell Library
Granted: January 10, 2013
Application Number:
20130013276
A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the…
CURRENT SOURCE WITH LOW POWER CONSUMPTION AND REDUCED ON-CHIP AREA OCCUPANCY
Granted: January 3, 2013
Application Number:
20130002228
A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit.…
Extending Processor MMU for Shared Address Spaces
Granted: January 3, 2013
Application Number:
20130007407
A system and a method are disclosed for more efficiently handling shared code stored in memory, comprising a modified memory management unit containing a new shared address space identifier register, and a modified TLB entry containing a new shared bit.
MEMORY ARBITER WITH LATENCY GUARANTEES FOR MULTIPLE PORTS
Granted: January 3, 2013
Application Number:
20130007386
Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of…
Determining Calibration Parameters For a Lithographic Process
Granted: January 3, 2013
Application Number:
20130004056
A technique for determining a set of calibration parameters for use in a model of a photo-lithographic process is described. In this calibration technique, images of a test pattern that was produced using the photo-lithographic process are used to determine corresponding sets of calibration parameters. These images are associated with at least three different focal planes in an optical system, such as a photo-lithographic system that implements the photo-lithographic process. Moreover,…
HIGH VOLTAGE REGULATION IN CHARGE PUMPS
Granted: January 3, 2013
Application Number:
20130002343
High voltage regulation in charge pumps. A circuit includes a voltage regulator with a first input in communication with a reference voltage. The circuit also includes a data latch having a signal input coupled to receive an output of the voltage regulator and coupled to receive a clock input from a clock source. The circuit further includes a delay circuit having an input coupled to receive the clock input from the clock source. Further, the circuit includes a logic gate having a first…
Reducing Leakage Power in Integrated Circuit Designs
Granted: December 20, 2012
Application Number:
20120324412
A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative…
INTEGRATED CIRCUIT OPTIMIZATION MODELING TECHNOLOGY
Granted: December 20, 2012
Application Number:
20120324411
A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target…
AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANALYSIS
Granted: December 20, 2012
Application Number:
20120324410
Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but…
Single-Ended-To-Differential Filter Using Common Mode Feedback
Granted: December 20, 2012
Application Number:
20120319767
A filter including common mode feedback can provide single-ended to differential-ended conversion with minimum loss of performance.
METHOD AND APPARATUS FOR PERFORMING VIA ARRAY MERGING AND PARASITIC EXTRACTION
Granted: December 13, 2012
Application Number:
20120317531
Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M?2, N?2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively;…
FRACTIONAL FREQUENCY DIVISION OR MULTIPLICATION USING AN OVERSAMPLED PHASE ROTATOR
Granted: November 22, 2012
Application Number:
20120294336
Circuits and systems for generating multiple frequencies are disclosed. In some embodiments, a circuit can include a first node, a second node, and a programmable phase rotator. The first node can receive a first signal having frequency f1, and the second node can output a second signal having frequency f2 that is different from f1. In some embodiments, a frequency divider can generate a third signal having frequency f3 based on the second signal. In some embodiments, a frequency divider…
ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS
Granted: November 22, 2012
Application Number:
20120295433
Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
