Multi-Threaded Global Routing
Granted: November 15, 2012
Application Number:
20120290997
A method is described for routing a semiconductor chip's global nets. The method includes identifying a subset of the global nets and routing the subset of global nets using multiple threads, where, each of the global nets within the subset are routed by one of the threads in isolation of the subset's other global nets. The method further includes identifying a second subset of the global nets and routing the second subset of global nets using the multiple threads, where, each of the…
METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES
Granted: November 8, 2012
Application Number:
20120280354
An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an…
EUV LITHOGRAPHY FLARE CALCULATION AND COMPENSATION
Granted: November 8, 2012
Application Number:
20120284675
Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes…
Relative Positioning of Circuit Elements in Circuit Design
Granted: November 8, 2012
Application Number:
20120284682
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING USING MULTIPLE VALUE SYSTEMS DURING CONSTRAINT SOLVING
Granted: November 1, 2012
Application Number:
20120278675
Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple…
Accelerating Coverage Convergence Using Symbolic Properties
Granted: October 18, 2012
Application Number:
20120266118
In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from…
Power Routing in Standard Cell Designs
Granted: October 4, 2012
Application Number:
20120249182
A cell-based architecture for an integrated circuit. A row of cell instances borders a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along a second boundary. A first power rail (e.g., carrying an auxiliary voltage) extends along the first boundary. A second power rail (e.g., VSS) extends along the second boundary. The second power rail is wider than the first power rail. Additionally, a third power rail (e.g., VDD) extends across…
METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS
Granted: October 4, 2012
Application Number:
20120253754
Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets…
Cell Architecture for Increasing Transistor Size
Granted: October 4, 2012
Application Number:
20120254817
A cell-based architecture for an integrated circuit that uses at least two categories of cells: cut-gate cells and breaker cells. Cut-gate cells have gates that extend from one boundary of the cell to an opposite boundary of the cell. Cut gate features are located along the boundaries of the cell to indicate locations for cutting the gates during fabrication. Instances of the cut-gate cells are arranged in abutting rows that result in the formation of continuous gate strips during the…
Pin Routing in Standard Cells
Granted: September 27, 2012
Application Number:
20120241986
Cells designed to accommodate metal routing tracks having a pitch that is an odd multiple of a manufacturing grid. The cells includes cell pins that are located within the cell based on the offsets of the routing tracks relative to the cell boundaries. The cell pins are wider than wires that are routed along the metal routing tracks. The standard cell may be placed in a layout in either a normal orientation or in a flipped orientation. In both orientations, the cell pins are aligned with…
METHOD AND APPARATUS FOR SYNTHESIZING CIRCULAR DECOMPRESSORS
Granted: September 20, 2012
Application Number:
20120239995
Methods and apparatuses are described for decompressing and routing test data. Some embodiments feature an integrated circuit (IC) that includes two or more shift registers configured to shift in the test data. Each of the two or more shift registers can include two or more sequential elements configured such that a scan chain in the set of scan chains receives inputs from at most one sequential element in each of the two or more shift registers. At least one shift register in the two or…
METHOD AND DEVICE FOR REORDERING SCAN CHAINS CONSIDERING PLAN GROUPS
Granted: September 20, 2012
Application Number:
20120240092
Provided in the present invention is a reconfiguration method and device for scan chains with the planned unit taken into consideration, wherein said reconfiguration method of the scan chains comprises a first phase reconfiguration and second phase reconfiguration. Said first phase reconfiguration first classifies a number of scan chains, wherein scan chains with the starting point and the ending point in the same planned unit are classified as a first aggregation of scan chains; scan…
MODELING EUV LITHOGRAPHY SHADOWING EFFECT
Granted: September 20, 2012
Application Number:
20120240086
Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.
Power Routing in Standard Cells
Granted: September 6, 2012
Application Number:
20120223368
An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and…
Integrated Circuit Arrangement for Buffering Service Requests
Granted: September 6, 2012
Application Number:
20120226826
The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (110) is arranged…
Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation
Granted: September 6, 2012
Application Number:
20120227022
An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of…
METHOD AND APPARATUS FOR DETERMINING A SUBSET OF TESTS
Granted: August 30, 2012
Application Number:
20120221283
Methods and apparatuses are described for determining a small subset of tests that provides substantially the same coverage as the set of tests. During operation, a system (e.g., a computer system) can determine a set of tests by, for each object in a set of objects, selecting up to a pre-determined number of tests that provide test coverage for the object. Next, the system can determine a subset of tests by iteratively performing a loop, which can comprise: selecting a test in the set…
Interactive Method and Apparatus for Detecting Texted Metal Short Circuits
Granted: August 30, 2012
Application Number:
20120221991
Methods and devices are disclosed herein to test the texted metal short circuit. One such method comprises: To input a circuit design file, wherein the circuit design file comprises the data of the layout pattern of the circuit design, the file format of the circuit design is a generic data stream format; to input a set of design rules; to select a specific check rule based on the set of design rules, wherein the specific check rule is for testing the texted metal short circuit in the…
CONTROLLING A NON-VOLATILE MEMORY
Granted: August 23, 2012
Application Number:
20120213007
Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of memory cells. Moreover, the non-volatile memory includes a counter-doped-gate device, coupled within…
PARTITIONING PAGES OF AN ELECTRONIC MEMORY
Granted: August 23, 2012
Application Number:
20120215962
A method of partitioning a page of an electronic memory includes creating a first sub-page by interleaving a first user data section of the page with another section of a spare area of the page excluding a specified address in a section of the spare area that stores a bad block marker. The method also includes creating the sub-pages by interleaving the user data sections with sections of the spare area excluding the specified address until a last sub-page is to be created. Further, the…
