Routing Method for Flip Chip Package and Apparatus Using the Same
Granted: August 23, 2012
Application Number:
20120216167
Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between…
Method and Apparatus Used for the Physical Validation of Integrated Circuits
Granted: August 23, 2012
Application Number:
20120216162
Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison.
Very Dense NVM Bitcell
Granted: August 16, 2012
Application Number:
20120205734
An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby…
Method and System for Lithography Hotspot Correction of a Post-Route Layout
Granted: August 16, 2012
Application Number:
20120210280
Disclosed herein are correcting methods and devices for lithography hotspots of the post-routing layout, used for correcting lithography hotspots detected in the post-routing layout. At least one two-dimensional pattern of changeable size or position of the number of hotspots in the local area is selected and adjusted, so that the simulation value of the aerial image intensity of various local areas is optimized. The simulation value of the aerial image intensity is derived through…
Method and Device for Reconstructing Scan Chain Based on Bidirectional Preference Selection in Physical Design
Granted: August 16, 2012
Application Number:
20120210290
Reconstruction methods and devices are disclosed for scan chains in physical design that is based on two-way priority selection. The structural reconstruction method in the scan chains, in the first place, establishes a first preference sequence for a certain number of scanning elements in each of these scan chains as well as a secondary preference sequence for these scan chains in each of these scanning elements respectively. Then, two-way selection is executed between the scan chains…
HDMI Controller Circuit For Transmitting Digital Data To Compatible Audio Device Using Address Decoder Where Values Are Written To Registers Of Sub-Circuits
Granted: August 9, 2012
Application Number:
20120200771
The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the…
MULTIVOLTAGE CLOCK SYNCHRONIZATION
Granted: August 2, 2012
Application Number:
20120194255
A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or…
GPS Baseband Architecture
Granted: August 2, 2012
Application Number:
20120194384
A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer with a frequency to convert a signal to a higher intermediate (IF) frequency. The output of the mixer is fed to a poly-phase filter. The output of the poly-phase filter is fed to a programmable gain amplifier (PGA), whose…
ABSTRACTION-BASED LIVELOCK/DEADLOCK CHECKING FOR HARDWARE VERIFICATION
Granted: August 2, 2012
Application Number:
20120198397
Some embodiments of the present invention provide systems and techniques for checking a livelock in a circuit design. During operation, the system can identify a finite state machine (FSM) in the circuit design, wherein the FSM comprises a first set of state variables. The system can then construct an abstract machine of the circuit design, wherein the abstract machine includes the FSM and a second set of state variables. Next, the system can search for one or more livelocks in the…
Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integrated Circuit Net Assignment
Granted: August 2, 2012
Application Number:
20120198409
A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths…
INSTRUCTION-SET ARCHITECTURE SIMULATION TECHNIQUES USING JUST IN TIME COMPILATION
Granted: June 21, 2012
Application Number:
20120158397
A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the…
Simultaneous Multi-Corner Static Timing Analysis Using Samples-Based Static Timing Infrastructure
Granted: June 21, 2012
Application Number:
20120159414
A method of performing simultaneous multi-corner static timing analysis (STA) on a design for an integrated circuit is provided. This method can include reading design data including a netlist, parasitics, and libraries at a plurality of corners. Each corner can represent a set of process, temperature, and voltage conditions. Using the design data as inputs, a plurality of operations can be performed to generate timing reports regarding the design at the plurality of corners. Notably,…
HIGH PERFORMANCE DRC CHECKING ALGORITHM FOR DERIVED LAYER BASED RULES
Granted: June 7, 2012
Application Number:
20120144349
Roughly described, a design rule data set includes rules on derived layers. The rules are checked by traversing the corners of physical shapes, and for each corner, populating a layout topology database with values gleaned from that corner location, including values involving derived layers. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations, including violations of design rules defined on…
HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE
Granted: June 7, 2012
Application Number:
20120144355
Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be…
METHOD AND APPARATUS FOR OPTIMIZING CONSTRAINT SOLVING THROUGH CONSTRAINT REWRITING AND DECISION REORDERING
Granted: May 31, 2012
Application Number:
20120136635
Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking…
METHOD AND APPARATUS FOR DETERMINING MASK LAYOUTS FOR A SPACER-IS-DIELECTRIC SELF-ALIGNED DOUBLE-PATTERNING PROCESS
Granted: May 31, 2012
Application Number:
20120137261
Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is…
METHOD AND APPARATUS FOR FIXING DESIGN REQUIREMENT VIOLATIONS IN MULTIPLE MULTI-CORNER MULTI-MODE SCENARIOS
Granted: May 24, 2012
Application Number:
20120131525
Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one…
TARGETED PRODUCTION CONTROL USING MULTIVARIATE ANALYSIS OF DESIGN MARGINALITIES
Granted: May 24, 2012
Application Number:
20120131527
Targeted production control using multivariate analysis of design marginalities. A list of a plurality of metrology operations is accessed during production of an integrated circuit device. The list is generated from operations performed in the design of the integrated circuit device. At least one of the plurality of metrology operations is performed on the integrated circuit device. A manufacturing process of the integrated circuit device may be adjusted responsive to results of the…
Reducing Leakage Power in Integrated Circuit Designs
Granted: May 24, 2012
Application Number:
20120131531
A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative…
METHOD AND APPARATUS FOR EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION
Granted: May 17, 2012
Application Number:
20120123763
One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a…
