Generating Hardware Accelerators and Processor Offloads
Granted: May 17, 2012
Application Number:
20120124588
System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware…
Data Recovery Architecture (CDR) For Low-Voltage Differential Signaling (LVDS) Video Transceiver Applications
Granted: May 3, 2012
Application Number:
20120106688
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.
PFET Nonvolatile Memory
Granted: April 26, 2012
Application Number:
20120099380
A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage…
EFFICIENT CLOCK MODELS AND THEIR USE IN SIMULATION
Granted: April 26, 2012
Application Number:
20120101798
Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used.
METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES
Granted: April 12, 2012
Application Number:
20120086068
A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate.
HIGH-VOLTAGE SWITCH USING THREE FETS
Granted: April 12, 2012
Application Number:
20120086498
Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that…
Secure Provisioning of Resources in Cloud Infrastructure
Granted: April 5, 2012
Application Number:
20120084847
Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. The provisioning of resources is handled by a cloud provisioning system that is generally operated and maintained by an EDA tool developer using a provisioning credential. After the resources are provisioned, the cloud provisioning system places user key on the provisioned resources. Once the user key is placed on the provisioned…
Nonlinear Approach to Scaling Circuit Behaviors for Electronic Design Automation
Granted: March 29, 2012
Application Number:
20120079441
Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based on the data and operating conditions in the library set. These parameters and nonlinear transforms can then be used to scale circuit…
Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor
Granted: March 22, 2012
Application Number:
20120072879
Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.
METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULATION AND VERIFICATION
Granted: March 22, 2012
Application Number:
20120072876
Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the…
Parallel Parasitic Processing In Static Timing Analysis
Granted: March 15, 2012
Application Number:
20120066656
A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect…
Non-Linear Rasterized Contour Filters
Granted: March 8, 2012
Application Number:
20120060132
A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values in the second image is determined. The contribution is selected from a set of pre-determined contributions that are a nonlinear function of the values in the region, and the selection is made…
SYSTEMS AND METHODS FOR RESOURCE CONTROLLING
Granted: March 8, 2012
Application Number:
20120060169
A resource controller that includes a first buffer configured to store requests of a first predefined category having a first priority. In addition, the resource controller includes at least a second buffer configured to store requests of a second predefined category having a second priority where the first priority is set such that processing requests of the first category has priority over processing the requests of the second category. Also, the resource controller includes a…
INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA
Granted: March 1, 2012
Application Number:
20120054693
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the…
Group Management Using Unix NIS Groups
Granted: February 16, 2012
Application Number:
20120041984
In one implementation, a system for managing Groups in a Unix environment includes a group management engine and an NIS converter. A group information database stores information about Groups and their Members. The group management engine receives commands from Administrators of a Group to change attributes of Members in the Group. It accesses the database and makes the requested changes. The information in the database is not in an NIS-compatible format. The NIS converter accesses the…
Method and Apparatus for Automatic Relative Placement Rule Generation
Granted: February 9, 2012
Application Number:
20120036488
Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.
PERFORMING SCENARIO REDUCTION USING A DOMINANCE RELATION ON A SET OF CORNERS
Granted: February 2, 2012
Application Number:
20120030641
Some embodiments of the present invention provide techniques and systems for performing scenario reduction using a dominance relation on a set of corners. During operation, the system can receive a design library which specifies gate characteristics at each corner in a set of corners. Next, the system can use the design library to determine a dominance relation on the set of corners for each gate type. The dominance relations can be stored with the design library. The system can then…
HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION
Granted: February 2, 2012
Application Number:
20120030642
Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the…
DC-DC Converter
Granted: January 26, 2012
Application Number:
20120019224
A dual-mode switching voltage regulator has a duty cycle that varies with the input and output voltages so as to dynamically compensate for changes in the operating conditions. The switching voltage regulator uses input and output voltages/currents to optimize the duty cycle of the signals applied to a pair of switches disposed in the regulator. In the PFM mode, a control block senses the time that a first switch used to discharge an inductor is turned off. If the control block senses…
BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS
Granted: January 12, 2012
Application Number:
20120011479
Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel…
