HIGHLY FLEXIBLE FRACTIONAL N FREQUENCY SYNTHESIZER
Granted: December 22, 2011
Application Number:
20110310942
One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock…
METHOD AND APPARATUS FOR PERFORMING ADAPTIVE EQUALIZATION
Granted: December 22, 2011
Application Number:
20110310947
Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each…
PATTERN AGNOSTIC ON-DIE SCOPE
Granted: December 22, 2011
Application Number:
20110311009
An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can…
CIRCUITRY FOR MATCHING THE UP AND DOWN IMPEDANCES OF A VOLTAGE-MODE TRANSMITTER
Granted: December 22, 2011
Application Number:
20110309857
Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the…
Efficient Data Compression For Vector-Based Static Timing Analysis
Granted: December 15, 2011
Application Number:
20110307226
In a STA method, after accessing data sets regarding the IC, vectors of the data sets for STA can be generated. Each vector can include a base value and a plurality of tokens, wherein each token is quantized. For each vector, the data of the vector can be adjusted. Adjusting can include shifting a predetermined token to zero and adjusting the base value and remaining token values based on the shifting. Incremental compression can be applied within the vector by storing each token value…
REDUCING POWER CONSUMPTION IN CLOCK AND DATA RECOVERY SYSTEMS
Granted: December 15, 2011
Application Number:
20110307722
Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The…
RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS
Granted: December 15, 2011
Application Number:
20110307850
A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the…
METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION
Granted: December 8, 2011
Application Number:
20110302546
Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be associated with a process corner, an operating condition, and/or an operating mode. During operation, the system can receive a set of scenarios over which the circuit design is to be optimized. Next, the system can compute values of constrained objects in the circuit design over the set of…
METHOD AND APPARATUS FOR USING SCENARIO REDUCTION IN A CIRCUIT DESIGN FLOW
Granted: December 8, 2011
Application Number:
20110302547
Some embodiments of the present invention provide techniques and systems for using scenario reduction in a design flow. The system can use scenario reduction to determine two subsets of scenarios that correspond to two sets of design constraints. Next, the system can optimize the circuit design using one of the sets of design constraints over the associated subset of scenarios. Next, the system can optimize the circuit design using both sets of design constraints over the union of the…
CIRCUITRY TO FACILITATE TESTING OF SERIAL INTERFACES
Granted: December 8, 2011
Application Number:
20110302452
Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the…
Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization
Granted: December 8, 2011
Application Number:
20110301907
Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention…
Electrostatic Discharge Management Apparatus, Systems, and Methods
Granted: December 8, 2011
Application Number:
20110298051
Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source…
MULTIPLE-INPUT, ON-CHIP OSCILLOSCOPE
Granted: December 1, 2011
Application Number:
20110292990
An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of…
METHOD AND APPARATUS FOR CUSTOM MODULE GENERATION
Granted: December 1, 2011
Application Number:
20110296364
Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one…
GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT
Granted: November 24, 2011
Application Number:
20110289464
Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the…
Method and Apparatus for Merging EDA Coverage Logs of Coverage Data
Granted: November 17, 2011
Application Number:
20110283246
An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second…
FORMAL EQUIVALENCE CHECKING BETWEEN TWO MODELS OF A CIRCUIT DESIGN USING CHECKPOINTS
Granted: November 10, 2011
Application Number:
20110276934
Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM…
CONTEXT-BASED EVALUATION OF EQUATIONS
Granted: November 10, 2011
Application Number:
20110276947
Some embodiments provide a system that facilitates the evaluation of an equation. During operation, the system obtains one or more data-access functions to be used in the equation. Next, the system obtains an analysis context for the equation separately from the data-access functions. The analysis context may include one or more analysis parameters that specify one or more data sources and/or types of analysis to be used in evaluating the equation. Finally, the system evaluates the…
Non-Volatile Memory Cell with BTBT Programming
Granted: October 20, 2011
Application Number:
20110255348
A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.
Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry
Granted: October 20, 2011
Application Number:
20110258498
A test architecture is described that adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values.
