Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques
Granted: October 20, 2011
Application Number:
20110258503
Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows.…
COMPARING TIMING CONSTRAINTS OF CIRCUITS
Granted: October 13, 2011
Application Number:
20110252388
Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing…
AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS
Granted: October 13, 2011
Application Number:
20110252390
Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are…
AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS
Granted: October 13, 2011
Application Number:
20110252393
Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are…
EFFICIENT PROVISIONING OF RESOURCES IN PUBLIC INFRASTRUCTURE FOR ELECTRONIC DESIGN AUTOMATION (EDA) TASKS
Granted: October 6, 2011
Application Number:
20110246653
Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. Performance metrics of servers in the public cloud infrastructure and performance history of a user's past EDA tasks are maintained to estimate operation parameters such as runtime of a new EDA task. Based on the estimation, a user can provision appropriate types and amounts of resources in the public cloud infrastructure in a…
ROUTING AND DELIVERY OF DATA FOR ELECTRONIC DESIGN AUTOMATION WORKLOADS IN GEOGRAPHICALLY DISTRIBUTED CLOUDS
Granted: October 6, 2011
Application Number:
20110246997
Electronic design automation (EDA) libraries are delivered using a geographically distributed private cloud including EDA design centers and EDA library stores. EDA projects associated with an EDA library are determined by matching information describing the EDA library with information describing the projects. A set of design centers hosting the projects is determined. A data delivery model is determined for transmitting the EDA library to the design centers. The EDA library is…
Client/Server Waveform Viewer Using Bitmaps
Granted: September 29, 2011
Application Number:
20110234600
Improving on the waveform viewing technology can advantageously address the industry's need for speedup and capacity of existing solution. As described herein, making data manipulation local and bounded can facilitate tremendous speedup. The waveform viewer can process data on-demand where the user explicitly specifies signals and a desired window (i.e. range). Operations including, but not limited to, zoom, pan, scan, etc. on the waveform viewer can be sent to the waveform servers in…
Increasing PRPG-Based Compression by Delayed Justification
Granted: September 22, 2011
Application Number:
20110231805
An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines,…
MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION
Granted: September 22, 2011
Application Number:
20110231811
An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is…
Fast Photolithography Process Simulation to Predict Remaining Resist Thickness
Granted: September 15, 2011
Application Number:
20110224963
A lithography model uses a transfer function to map exposure energy dose to the thickness of remaining photoresist after development; while allowing the flexibility to account for other physical processes. In one approach, the model is generated by fitting empirical data. The model may be used in conjunction with an aerial image to obtain a three-dimensional profile of the remaining photoresist thickness after the development process. The lithography model is generally compact, yet…
Mixed Concurrent And Serial Logic Simulation Of Hardware Designs
Granted: September 8, 2011
Application Number:
20110218792
A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of…
Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit
Granted: September 8, 2011
Application Number:
20110219351
An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout…
PARAMETERIZED CELL CACHING IN ELECTRONIC DESIGN AUTOMATION
Granted: September 8, 2011
Application Number:
20110219349
Some embodiments provide a system that improves performance during parameterized cell instantiation in an electronic design automation (EDA) application. During operation, the system persists evaluation results associated with a parameterized cell in the design within a session of the EDA application so that the evaluation results are available even after they have been flushed from memory. Further, the system can persist the evaluation results across sessions of the EDA application.…
Stress-Enhanced Performance Of A Finfet Using Surface/Channel Orientations And Strained Capping Layers
Granted: September 1, 2011
Application Number:
20110212601
Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a…
EVALUATING THE QUALITY OF AN ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD
Granted: August 18, 2011
Application Number:
20110202891
One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target…
Active Net Based Approach for Circuit Characterization
Granted: August 11, 2011
Application Number:
20110197170
In a circuit design method, a computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a limited part of the circuit design, where the limited part determined by the active nets. The computer system performs simulation of the circuit design including the netlist of a circuit design and the parasitic netlist of the limited part of the circuit…
ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION
Granted: August 4, 2011
Application Number:
20110191731
Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on…
METHOD AND APPARATUS FOR DETERMINING A ROBUSTNESS METRIC FOR A CIRCUIT DESIGN
Granted: August 4, 2011
Application Number:
20110191732
Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new…
DENSITY-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION
Granted: August 4, 2011
Application Number:
20110191738
Some embodiments provide techniques and systems for improving the efficiency of area recovery in an electronic design automation (EDA) flow. During operation, the system determines a utilization of a region from a set of regions in a design floorplan. Next, the system performs area recovery (e.g., by using a processor) on the region based at least on the utilization. Specifically, the system can overlay the design floorplan with a grid, wherein the grid comprises a set of grid cells and…
ZONE-BASED OPTIMIZATION FRAMEWORK
Granted: August 4, 2011
Application Number:
20110191740
Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the…
