GENERATING EQUATIONS BASED ON USER INTENT
Granted: July 28, 2011
Application Number:
20110185307
Some embodiments provide a system that facilitates the creation of an equation. During operation, the system obtains a user selection of a function to be used in the equation. Next, the system determines a state of a graphical user interface (GUI) associated with a software program. More specifically, the system may determine a cursor position or a text selection in the equation. Finally, the system facilitates the creation of the equation by inserting the function into the equation…
METHOD AND APPARATUS FOR CALIBRATING A PHOTOLITHOGRAPHY PROCESS MODEL BY USING A PROCESS WINDOW PARAMETER
Granted: July 28, 2011
Application Number:
20110185324
One embodiment of the present invention relates to a system that calibrates a photolithography process model. During operation, the system receives a process model which models a photolithography process. The system further receives measured critical dimension (CD) values for a first set of features that were printed by applying the photolithography process to a layout. The system then calibrates the process model using the measured CD values so that CD values predicted by the process…
GENERATING AND USING ROUTE FIX GUIDANCE
Granted: July 28, 2011
Application Number:
20110185329
Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation.…
GLOBAL LEAKAGE POWER OPTIMIZATION
Granted: July 28, 2011
Application Number:
20110185333
Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the…
ZONE-BASED LEAKAGE POWER OPTIMIZATION
Granted: July 28, 2011
Application Number:
20110185334
A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times…
DETERMINING AN ORDER FOR VISITING CIRCUIT BLOCKS IN A CIRCUIT DESIGN FOR FIXING DESIGN REQUIREMENT VIOLATIONS
Granted: July 28, 2011
Application Number:
20110185335
Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners…
OPTIMIZING BOUNDS CHECKING USING COMPUTER ALGEBRA
Granted: July 28, 2011
Application Number:
20110185341
Some embodiments of the present invention provide techniques and systems for optimizing bounds-checking During operation, the system can receive one or more instructions which when executed evaluate a first expression whose value is required to be between a lower bound expression's value and an upper bound expression's value, such that at least one of the following three values is not determinable before execution: the first expression's value, the lower bound expression's value, and the…
METHOD AND APPARATUS FOR USING AERIAL IMAGE SENSITIVITY TO MODEL MASK ERRORS
Granted: July 28, 2011
Application Number:
20110184546
One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent…
ETCH-AWARE OPC MODEL CALIBRATION BY USING AN ETCH BIAS FILTER
Granted: July 21, 2011
Application Number:
20110179393
One embodiment of the present invention relates to a system that constructs and calibrates an etch-aware photolithography model. During operation, the system constructs an etch bias model which models a critical dimension (CD) difference between a measured CD value of a feature after the photolithography process and a measured CD value of the feature after the etch process. The system then fits the photolithography process model based at least on the post-lithography measured CD data and…
Nonlinear Driver Model For Multi-Driver Systems
Granted: July 14, 2011
Application Number:
20110173580
A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate…
RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS
Granted: July 14, 2011
Application Number:
20110169140
Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via…
METHOD AND APPARATUS FOR SIMULATING BEHAVIORAL CONSTRUCTS USING INDETERMINATE VALUES
Granted: June 30, 2011
Application Number:
20110161897
One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an…
Non Volatile Memory Circuit With Tailored Reliability
Granted: June 23, 2011
Application Number:
20110147469
A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might…
OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION
Granted: June 16, 2011
Application Number:
20110140278
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for…
CONVOLUTION COMPUTATION FOR MANY-CORE PROCESSOR ARCHITECTURES
Granted: June 9, 2011
Application Number:
20110138157
A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set,…
METHOD AND APPARATUS FOR PRESENTING DATE IN A TABULAR FORMAT
Granted: June 9, 2011
Application Number:
20110138265
Some embodiments provide a system for displaying cells of a table. During operation, the system can receive a sort-and-merge request for sorting the rows of the table using a sort column. Next, the system can sort the rows of the table based at least on cell values in the sort column to obtain a sorted table. The system can then merge a set of consecutive cells in a merge column of the sorted table to obtain a merged cell, wherein the set of consecutive cells are associated with the same…
Path Preserving Design Partitioning With Redundancy
Granted: June 2, 2011
Application Number:
20110131540
Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA. Once these…
Multi-Mode Redundancy Removal
Granted: May 26, 2011
Application Number:
20110126167
A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the…
Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (IC) Design
Granted: May 19, 2011
Application Number:
20110119531
Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.
DRAWING AN IMAGE WITH TRANSPARENT REGIONS ON TOP OF ANOTHER IMAGE WITHOUT USING AN ALPHA CHANNEL
Granted: May 5, 2011
Application Number:
20110102456
An image display system draws a first image on top of a second image. Pixels of the first image include one or more color channels which encode color information, but do not include an alpha channel which encodes transparency information. The system encodes transparency information for the pixels in the first image using at least one bit in at least one color channel of each pixel. The system draws the first image on top of the second image using the transparency information encoded in…
