TECHNIQUE FOR GENERATING AN ANALYSIS EQUATION
Granted: May 5, 2011
Application Number:
20110107252
During a method, a hybrid graphical user interface (GUI), which is associated with electronic-design-automation (EDA) software, is displayed. This hybrid GUI allows users to efficiently specify useful analysis equations using textual and/or graphical information. In particular, the hybrid GUI has a first window that includes graphical objects associated with a circuit design. A user can select one or more of the graphical objects and associated electrical parameters using a…
TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION
Granted: May 5, 2011
Application Number:
20110107281
Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further…
METHOD AND APPARATUS FOR LEGALIZING A PORTION OF A CIRCUIT LAYOUT
Granted: May 5, 2011
Application Number:
20110107286
A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion…
SIMULATION-BASED DESIGN STATE SNAPSHOTTING IN ELECTRONIC DESIGN AUTOMATION
Granted: May 5, 2011
Application Number:
20110107293
Some embodiments provide a system that performs a simulation within an electronic design automation (EDA) application. During operation, the system obtains a design from a user of the EDA application. Next, the system performs the simulation using the design to create a set of current simulation results associated with the design. The system then automatically saves a current design state of the design which is associated with the current simulation results. Finally, the system enables…
TECHNIQUE FOR DYNAMICALLY SIZING COLUMNS IN A TABLE
Granted: May 5, 2011
Application Number:
20110107196
During a technique for dynamically determining sizes of columns in a table, available space in the table is allocated based at least on sequential groups of size targets, which include ranges of sizes of the columns, and which are associated with ordered visual usability targets for the columns. Note that a given size target in a given group of size targets includes a given range of sizes of a given column. For example, minimum sizes of the columns may correspond to the ranges of sizes…
ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS
Granted: April 28, 2011
Application Number:
20110095367
Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
"Supply-Less" HDMI Source Terminated Output Stage With Tuned Wide-Range Programmable Termination
Granted: April 28, 2011
Application Number:
20110096848
A “supply-less” transmitter output stage is provided for a transmitter. This transmitter output stage can include a tunable source termination and a reference voltage generator. The tunable source termination can be coupled between a differential pair of the transmitter. The reference voltage generator can advantageously generate reference voltages from a far-end termination. These reference voltages provide a way of translating the internal supply voltage level to the pad voltage…
Method and Apparatus for Synthesis of Augmented Multimode Compactors
Granted: April 21, 2011
Application Number:
20110093752
Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.
Integrated Circuit Optimization Modeling Technology
Granted: April 21, 2011
Application Number:
20110093830
A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target…
FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM
Granted: March 31, 2011
Application Number:
20110078639
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an…
RIPPLED MIXERS FOR UNIFORMITY AND COLOR MIXING
Granted: March 10, 2011
Application Number:
20110058388
Various embodiments described herein comprise mixers comprising a light pipe having input and output ends and a central region therebetween. An optical path extends in a longitudinal direction from the input end through the central region to the output end. The central region of the light pipe comprises one or more rippled reflective sidewalls having a plurality of elongate ridges and valleys and sloping surfaces therebetween. Light from the input end propagating along the optical path…
Pre-Route And Post-Route Net Correlation With Defined Patterns
Granted: March 10, 2011
Application Number:
20110061038
A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching…
Generating Net Routing Constraints For Place And Route
Granted: March 10, 2011
Application Number:
20110061037
A method of generating net routing constraints for nets of an IC design includes generating a file with hashes organized by nets. Each hash has attributes of a net, e.g. net name, length, fanout, total actual route (AR) resistance, a corresponding virtual route (VR) resistance, and a number of vias. A wire only AR resistance for each net can be calculated. Wire scaling factors can be calculated using the wire only AR resistances and their corresponding VR resistances. Wire scaling…
MULTI-THREADED GLOBAL ROUTING
Granted: March 3, 2011
Application Number:
20110055784
Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During operation, the system determines bounding boxes for nets, and associates nets with partitions, wherein a partition associated with a net encloses the net's bounding box. Then, the system routes nets in non-overlapping partitions in parallel. Next, the system adjusts bounding boxes of nets which need to…
METHOD AND APPARATUS FOR PERFORMING REDUNDANT VIA INSERTION DURING CIRCUIT DESIGN
Granted: March 3, 2011
Application Number:
20110055785
One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via…
METHOD AND APPARATUS FOR SATISFYING ROUTING RULES DURING CIRCUIT DESIGN
Granted: March 3, 2011
Application Number:
20110055786
One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution. The system then assigns weights to the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule. The system additionally assigns…
METHOD AND APPARATUS FOR ROUTING USING A DYNAMIC GRID
Granted: March 3, 2011
Application Number:
20110055788
One embodiment of the present invention provides a system that routes connections in an integrated circuit (IC) chip design. The system includes a representation mechanism which is configured to represent routing resources in the IC chip design as a 3-dimensional (3D) grid. This 3D grid further includes: static grid lines which do not change while the system routes the connections; and dynamic grid lines which are created for routing a connection that includes pins which are not located…
MULTI-THREADED TRACK ASSIGNMENT
Granted: March 3, 2011
Application Number:
20110055789
Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a first set of partitions for a circuit design, wherein each partition in the first set of partitions extends across the circuit design along a first direction. Next, the system can perform, in parallel, track assignment in the first direction on non-overlapping partitions in the first set of partitions. The system can then receive a second set of…
MULTI-THREADED DETAILED ROUTING
Granted: March 3, 2011
Application Number:
20110055790
Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a set of partitions for a circuit design, wherein each partition has zero or more overlapping partitions along four directions, e.g., up, down, left, and right. Next, the system can perform, in parallel, detailed routing on non-overlapping partitions in the set of partitions, wherein detailed routing is performed on a partition after detailed routing…
METHOD AND APPARATUS FOR PERFORMING ROUTING OPTIMIZATION DURING CIRCUIT DESIGN
Granted: March 3, 2011
Application Number:
20110055791
One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing…
