Systemic Diagnostics For Increasing Wafer Yield
Granted: February 17, 2011
Application Number:
20110040528
A method of performing systemic diagnostics for a wafer includes selecting a design for manufacturability (DFM) rule for analysis. For each IC chip on the wafer, two sets of IC features adjacent the rule can be extracted based on the chip's layout design. Upconverted diagnostics can be run to generate computed numbers associated with combination categories for each set. Zonal analysis can be run on the two sets using the computed numbers to derive metrics for the two sets. A report can…
METHOD AND APPARATUS FOR GENERATING A MEMORY-EFFICIENT REPRESENTATION OF ROUTING DATA
Granted: February 17, 2011
Application Number:
20110041111
Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points, such that two consecutive points represent a routing shape. At least some of the points can be represented using a compact representation, thereby reducing the memory required for storing the sequence of points. A full…
METHOD AND APPARATUS FOR GENERATING A CENTERLINE CONNECTIVITY REPRESENTATION
Granted: February 17, 2011
Application Number:
20110041112
Some embodiments provide a system for generating a centerline connectivity representation for a set of routing shapes. During operation, the system can represent the set of routing shapes using a set of centerlines with endcap extensions. Note that an intersection between two centerlines represents an electrical connection between the two routing shapes associated with the two centerlines. Next, the system can detect two routing shapes which overlap, but whose centerlines do not…
METHOD FOR DYNAMICALLY ADJUSTING SPEED VERSUS ACCURACY OF COMPUTER PLATFORM SIMULATION
Granted: February 10, 2011
Application Number:
20110035201
Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also…
LOOP REMOVAL IN ELECTRONIC DESIGN AUTOMATION
Granted: February 3, 2011
Application Number:
20110025705
Some embodiments provide a system that facilitates graphical object creation in an electronic design automation (EDA) application. During operation, the system uses a cursor to obtain a sequence of points from a user for creating a graphical object in a layout. Next, the system detects a loop in the graphical object based at least on the sequence of points and a current position of the cursor. Finally, the system modifies the sequence of points to remove the loop from the graphical…
METHOD AND APPARATUS FOR MODELING CHEMICALLY AMPLIFIED RESISTS
Granted: February 3, 2011
Application Number:
20110029118
Some embodiments provide a system for accurately and efficiently modeling chemically amplified resist. During operation, the system can determine a quenched acid profile from an initial acid profile by applying multiple quenching models which are associated with different acid concentration ranges to the initial acid profile. One quenching model may be expressed as H=H0?B0, where H is an acid profile after quenching, H0 is an acid profile before quenching, and B0 is an initial base…
Hierarchical Order Ranked Simulation Of Electronic Circuits
Granted: February 3, 2011
Application Number:
20110029299
A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits…
METHOD AND APPARATUS FOR MODELING THIN-FILM TOPOGRAPHY EFFECT ON A PHOTOLITHOGRAPHY PROCESS
Granted: February 3, 2011
Application Number:
20110029940
One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector…
ROUTING VARIANTS IN ELECTRONIC DESIGN AUTOMATION
Granted: February 3, 2011
Application Number:
20110029944
Some embodiments provide a system that facilitates the creation of a schematic in an electronic design automation (EDA) application. During operation, the system obtains a source point and a destination point in the schematic from a user of the EDA application. Next, the system uses a line-probe-search technique to generate a set of route variants between the source point and the destination point. The system then provides the route variants to the user through a graphical user interface…
HDMI Controller Circuit For Transmitting Digital Data To Compatible Audio Device Using Address Decoder Where Values Are Written To Registers Of Sub-Circuits
Granted: January 27, 2011
Application Number:
20110019086
The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the…
CONNECTION NAVIGATION IN ELECTRONIC DESIGN AUTOMATION
Granted: January 27, 2011
Application Number:
20110023006
Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system obtains a set of parameters associated with parameterized connections in a hierarchy of the design and a set of net assignments to the parameters. Next, the system displays the parameters and the net assignments to a user of the EDA application through a graphical user interface (GUI) associated with the EDA application. Finally,…
DYNAMIC RULE CHECKING IN ELECTRONIC DESIGN AUTOMATION
Granted: January 27, 2011
Application Number:
20110023001
Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of the EDA application. Next, the system automatically applies a set of dynamic design rules to the schematic upon detecting the change. Finally, the system notifies the user of a rule violation if the schematic violates one or more of the dynamic design rules. The system allows the user to…
CYCLE-TAPPING TECHNIQUE FOR SELECTING OBJECTS
Granted: January 27, 2011
Application Number:
20110022987
A technique for selecting an object is described. During this technique, a computer system selects an object from multiple objects associated with a circuit design in an electronic-design-automation (EDA) environment based at least on a current cursor location and a current design command. For example, the computer system may select the object by determining distances between the cursor location and objects in at least a subset of the multiple objects, and then identifying the minimum…
USB 2.0 HS Voltage-Mode Transmitter With Tuned Termination Resistance
Granted: January 27, 2011
Application Number:
20110019763
A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to…
TRANSACTION HISTORY WITH BOUNDED OPERATION SEQUENCES
Granted: January 20, 2011
Application Number:
20110016094
A technique for maintaining a transaction history is described. This transaction history includes a sequence of commands or operations in an electronic-design-automation (EDA) environment. For subsets of one or more operations in the sequence of operations, the transaction history includes an associated transaction name, as well as a state of the of the subset, which is open after an initial EDA operation in the subset has been performed and is closed after a last EDA operation in the…
TECHNIQUE FOR REPLAYING OPERATIONS USING REPLAY LOOK-AHEAD INSTRUCTIONS
Granted: January 20, 2011
Application Number:
20110016294
A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation…
GENERATING WIDGETS FOR USE IN A GRAPHICAL USER INTERFACE
Granted: January 20, 2011
Application Number:
20110016423
During a technique for generating a window, a description of an object and associated attributes, which include information other than a visual presentation of the object, are received from a user. Then, different types of widgets are generated based at least on the description of the object, the attributes and predefined widget rules. These widgets are arranged in a window based at least on the widgets and predefined layout rules. For example, the widgets may be dynamically resized…
FLASH-BASED ANTI-ALIASING TECHNIQUES FOR HIGH-ACCURACY HIGH-EFFICIENCY MASK SYNTHESIS
Granted: January 20, 2011
Application Number:
20110016438
Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup…
Apparatus and Method of Delay Optimization
Granted: January 13, 2011
Application Number:
20110010680
Aspect of the technology are a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is for use in forming a lithographic mask set for use in fabricating an integrated circuit. In the method the computer system divides a synthesized circuit design into cell partitions along critical paths of the synthesized circuit design. The computer system associates pins of the plurality of cell partitions with normalized pin…
Multiplicative Division Circuit With Reduced Area
Granted: December 16, 2010
Application Number:
20100318592
The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one…
