Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers
Granted: November 18, 2010
Application Number:
20100291476
A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions…
Modeling critical-dimension (CD) scanning-electron-microscopy (CD-SEM) CD extraction
Granted: November 4, 2010
Application Number:
20100280812
One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during photolithography process model calibration. During operation, the process receives measured CD values which were obtained using a CD-SEM extraction process, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans. The process then…
LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS
Granted: November 4, 2010
Application Number:
20100280814
Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values…
MULTIPLE-POWER-DOMAIN STATIC TIMING ANALYSIS
Granted: November 4, 2010
Application Number:
20100281444
Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each power domain can be propagated during the full circuit graph-based STA to accurately perform STA without enumerating all paths. Some embodiments can use a…
EFFICIENT EXHAUSTIVE PATH-BASED STATIC TIMING ANALYSIS USING A FAST ESTIMATION TECHNIQUE
Granted: November 4, 2010
Application Number:
20100281445
One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one…
METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS
Granted: October 28, 2010
Application Number:
20100270597
Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the…
Method and Apparatus for Performing Stress Modeling of Integrated Circuit Material Undergoing Material Conversion
Granted: October 28, 2010
Application Number:
20100274376
A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material…
RUNTIME PROGRAMMABLE BIST FOR TESTING A MULTI-PORT MEMORY DEVICE
Granted: October 28, 2010
Application Number:
20100275074
One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access…
ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTATION
Granted: October 28, 2010
Application Number:
20100275169
Some embodiments provide a system for adaptively performing state-to-symbolic transformation in a canonical representation which is used for generating random stimulus for a constrained-random simulation. The system can construct a canonical representation for a set of constraints using the set of random variables and the subset of the state variables in the constraints. Next, the system can use the canonical representation to generate random stimulus for the constrained-random…
AUTOMATIC APPROXIMATION OF ASSUMPTIONS FOR FORMAL PROPERTY VERIFICATION
Granted: October 21, 2010
Application Number:
20100269078
One embodiment provides a system, comprising methods and apparatuses, for simplifying a set of assumptions for a circuit design, and for verifying the circuit design by determining whether the circuit design satisfies a set of assertions when the simplified set of assumptions is satisfied. During operation, the system can simplify the set of assumptions by identifying, for an assertion in the set of assertions, a first subset of assumptions which, either directly or indirectly, shares…
Model-based assist feature placement using inverse imaging approach
Granted: October 14, 2010
Application Number:
20100262946
Some embodiments provide techniques and systems to identify locations in a target mask layout for placing assist features. During operation, an embodiment can determine a spatial sampling frequency to sample the target mask layout, wherein sampling the target mask layout at the spatial sampling frequency prevents spatial aliasing in a gradient of a cost function which is used for computing an inverse mask field. Next, the system can generate a grayscale image by sampling the target mask…
EXECUTION MONITOR FOR ELECTRONIC DESIGN AUTOMATION
Granted: September 16, 2010
Application Number:
20100235795
Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can…
METHOD AND APPARATUS FOR GENERATING A FLOORPLAN USING A REDUCED NETLIST
Granted: September 16, 2010
Application Number:
20100235799
One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate…
METHOD AND APPARATUS FOR ACCELERATING PROJECT START AND TAPE-OUT
Granted: September 16, 2010
Application Number:
20100235801
Some embodiments of the present invention provide systems and techniques that accelerate project start and tape-out. During operation, a system can receive a set of technology files and a set of libraries. Next, the system can identify deficiencies in the set of technology files and the set of libraries. The system can then construct update utilities that when executed by a computer system cause the computer system to fix the deficiencies in the technology files and the set of libraries.…
STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS
Granted: September 9, 2010
Application Number:
20100229132
Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal…
CROSSTALK TIME-DELAY ANALYSIS USING RANDOM VARIABLES
Granted: September 9, 2010
Application Number:
20100229136
Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of…
Dynamically Reconfigurable Shared Scan-In Test Architecture
Granted: September 2, 2010
Application Number:
20100223516
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
METHOD AND APPARATUS FOR DETERMINING A PROCESS MODEL THAT MODELS THE IMPACT OF A CAR/PEB ON THE RESIST PROFILE
Granted: August 26, 2010
Application Number:
20100218160
An embodiment provides systems and techniques for determining a process model. During operation, the system may receive a first optical model which models a first optical system of a photolithography process. Next, the system may use the first optical model to determine a second optical model that models a second latent image that is formed by the first optical system at a second distance. The system may also use the first optical model to determine a third optical model that models a…
Class D Amplifier Having PWM Circuit With Look-Up Table
Granted: August 12, 2010
Application Number:
20100201445
A class D amplifier includes a noise-shaping modulator, a pulse width modulator, and a pulse amplifier. The noise-shaping modulator receive a pulse code modulated (PCM) signal and produces an oversampled PCM signal. The pulse width modulator produce a pulse width modulated (PWM) signal from the oversampled PCM signal. The pulse amplifier amplifies the PWM signal to produce an amplified PWM signal. The PWM uses a lookup table to convert from PCM to PWM. A compensation circuit optimizes…
METHOD AND SYSTEM FOR SIZING POLYGONS IN AN INTEGRATED CIRCUIT (IC) LAYOUT
Granted: August 5, 2010
Application Number:
20100194779
One embodiment of the present invention provides a system that sizes a polygon in a layout. During operation, the system receives a polygon which is to be sized by a sizing amount. The system then selects one or more vertices of the polygon. Next, the system replaces each selected vertex with a set of replacement vertices, and subsequently assigns a projection path to each replacement vertex in the set of replacement vertices. The system next performs a sizing operation on the polygon…
