INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA
Granted: August 5, 2010
Application Number:
20100198875
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the…
METHOD AND APPARATUS FOR PERFORMING RLC MODELING AND EXTRACTION FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D-IC) DESIGNS
Granted: August 5, 2010
Application Number:
20100199236
One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions,…
Non-Linear Receiver Model For Gate-Level Delay Calculation
Granted: August 5, 2010
Application Number:
20100199245
A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first…
METHOD AND APPARATUS FOR CORRECTING ASSIST-FEATURE-PRINTING ERRORS IN A LAYOUT
Granted: August 5, 2010
Application Number:
20100199255
One embodiment of the present invention provides a system that adjusts assist features in a layout to prevent assist features from printing. During operation, the system receives a layout. The system then identifies an assist-feature (AF)-printing hotspot in the layout, wherein the AF-printing hotspot includes a set of assist features and one or more target patterns in proximity to the set of assist features. At least one assist feature in the set of assist features is expected to print…
FAST AND ACCURATE ESTIMATION OF GATE OUTPUT LOADING
Granted: August 5, 2010
Application Number:
20100198539
Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output…
PERFORMING LOGIC OPTIMIZATION AND STATE-SPACE REDUCTION FOR HYBRID VERIFICATION
Granted: July 29, 2010
Application Number:
20100192111
One embodiment of the present invention provides a system that facilitates optimization and verification of a circuit design. The system can receive a set of assumptions associated with a circuit. The set of assumptions can specify a set of logical constraints on at least a set of primary inputs of the circuit. Note that the set of assumptions are expected to be satisfied during normal circuit operation. The system can generate a stimulus generator based in part on an assumption in the…
METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A LOWER-BOUND-DISTANCE
Granted: July 29, 2010
Application Number:
20100192114
Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used…
METHOD AND APPARATUS FOR MANAGING VIOLATIONS AND ERROR CLASSIFICATIONS DURING PHYSICAL VERIFICATION
Granted: July 29, 2010
Application Number:
20100192113
Some embodiments provide a system for managing violations during physical verification. The system may identify a design-rule-check (DRC) violation by applying a set of DRC rules to a layout. The system can then receive an error classification from the user which specifies how the DRC violation is to be handled. Next, the system can store the DRC violation, the user-selected error classification, and a user identifier associated with the user in a database. If the user is not authorized…
METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TEST SOLUTION
Granted: July 29, 2010
Application Number:
20100192030
Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the…
METHOD AND APPARATUS FOR CONSTRUCTING A CANONICAL REPRESENTATION
Granted: July 29, 2010
Application Number:
20100191679
Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR-size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a…
COMPACT ABBE'S KERNEL GENERATION USING PRINCIPAL COMPONENT ANALYSIS
Granted: July 29, 2010
Application Number:
20100191518
Some embodiments provide techniques for determining a set of Abbe's kernels which model an optical system of a photolithography process. During operation, the system can receive optical parameters (e.g., numerical aperture, wavelength, etc.) for the photolithography process's optical system. Next, the system can use the optical parameters to determine a point spread function for an Abbe's source. Note that the point spread function for the Abbe's source can be determined either by…
Power Network Stacked Via Removal For Congestion Reduction
Granted: July 29, 2010
Application Number:
20100190277
A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage…
BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS
Granted: July 29, 2010
Application Number:
20100187609
Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel…
Natural Language Assertion Processor
Granted: July 15, 2010
Application Number:
20100179804
A method of processing natural language assertions (NLAs) can include identifying an NLA and then translating that NLA into a verification language assertion (VLA) using a natural language parser (NLP) and synthesis techniques. This VLA can be translated into an interpreted NLA (NLA*) using a VLA parser and pattern matching techniques. At this point, the process can allow user review of the NLA* and the NLA. When the user determines that the NLA* and the NLA are the same or have…
MODELING MASK CORNER ROUNDING EFFECTS USING MULTIPLE MASK LAYERS
Granted: June 10, 2010
Application Number:
20100146476
An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then determine a set…
FAST LITHOGRAPHY COMPLIANCE CHECK FOR PLACE AND ROUTE OPTIMIZATION
Granted: May 27, 2010
Application Number:
20100131909
A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An…
METHOD AND APPARATUS FOR SCALING I/O-CELL PLACEMENT DURING DIE-SIZE OPTIMIZATION
Granted: May 27, 2010
Application Number:
20100131913
One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in…
Method and System for Enhancing the Yield In Semiconductor Manufacturing
Granted: May 13, 2010
Application Number:
20100121474
Roughly described, a manufacturing process is enhanced by using TCAD and TCAD-derived models. A TCAD simulation model of the process is developed, which predicts, in dependence upon a plurality of process input parameters, a value for a performance parameter of a product to be manufactured using the process. Estimated, predicted or desired values for a calculated subset of the parameters (including either process input parameters or product performance parameters or both), are determined…
USB 2.0 HS Voltage-Mode Transmitter With Tuned Termination Resistance
Granted: May 6, 2010
Application Number:
20100109706
A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to…
PROGRAMMABLE IF OUTPUT RECEIVER, AND APPLICATIONS THEREOF
Granted: May 6, 2010
Application Number:
20100110307
A tuner system for receiving a plurality of frequency bands includes a low noise amplifier coupled with a band selection filter to select a desired band. The tuner system further includes a complex RF filter to produce a complex RF signal from the selected band. The tuner system includes two double-quadrature converters, the first double-quadrature converter frequency down-converts the complex RF signal to a complex baseband signal. The complex baseband signal passes through a baseband…
