Shape-Based Geometry Engine To Perform Smoothing And Other Layout Beautification Operations
Granted: May 6, 2010
Application Number:
20100115481
A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or…
ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD
Granted: May 6, 2010
Application Number:
20100115486
One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target…
METHOD AND SYSTEM FOR PERFORMING LITHOGRAPHY VERIFICATION FOR A DOUBLE-PATTERNING PROCESS
Granted: May 6, 2010
Application Number:
20100115489
One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are…
METHOD AND APPARATUS FOR ALLOCATING RESOURCES IN A COMPUTE FARM
Granted: May 6, 2010
Application Number:
20100115526
Some embodiments provide a system for allocating resources in a compute farm. During operation, the system can receive resource-requirement information for a project. Next, the system can receive a request to execute a new job in the compute farm. In response to determining that no job slots are available for executing the new job, and that the project associated with the new job has not used up its allocated job slots, the system may execute the new job by suspending or re-queuing a job…
CONGESTION OPTIMIZATION DURING SYNTHESIS
Granted: May 6, 2010
Application Number:
20100115476
One embodiment of the present invention provides a system that optimizes a circuit design during a logic design stage to reduce routing congestion during a placement and routing stage. During operation, this system identifies a first circuit structure in the circuit design which is expected to cause routing congestion during the placement and routing stage. Next, the system generates a second circuit structure which is functionally equivalent to the first circuit structure, and is not…
Fast Simulation Method For Integrated Circuits With Power Management Circuitry
Granted: April 29, 2010
Application Number:
20100106476
In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and…
METHOD AND APPARATUS FOR MEMORY ABSTRACTION AND VERIFICATION USING SAME
Granted: April 29, 2010
Application Number:
20100107131
A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced.
METHOD AND APPARATUS FOR MEMORY ABSTRACTION AND FOR WORD LEVEL NET LIST REDUCTION AND VERIFICATION USING SAME
Granted: April 29, 2010
Application Number:
20100107132
A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The…
SECURE CONSULTATION SYSTEM
Granted: April 29, 2010
Application Number:
20100107220
A secure consultation system is disclosed that enables an owner entity to securely store its most secure and private data such that designated entities of the owner entity and a consultant entity can execute application programs on that data and thus, to consult on the operation and correctness of the application programs and the data.
Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques
Granted: April 22, 2010
Application Number:
20100100781
Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows.…
TWO-PHASE CLOCK-STALLING TECHNIQUE FOR ERROR DETECTION AND ERROR CORRECTION
Granted: April 22, 2010
Application Number:
20100097107
One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the…
METHOD AND APPARATUS FOR USING A SYNCHROTRON AS A SOURCE IN EXTREME ULTRAVIOLET LITHOGRAPHY
Granted: April 15, 2010
Application Number:
20100092880
One embodiment of the present invention provides a method to facilitate using a synchrotron as a source in an extreme ultraviolet lithography (EUVL) system, wherein the synchrotron's energy decreases over time. The EUVL system can includes a stepper which uses a step-and-repeat process or a step-and-scan process to transfer patterns from a reticle onto a wafer. The wafer is desired to be exposed to a substantially constant dose. During operation, the system can measure a synchrotron…
METHOD AND APPARATUS FOR DETERMINING A PHOTOLITHOGRAPHY PROCESS MODEL WHICH MODELS THE INFLUENCE OF TOPOGRAPHY VARIATIONS
Granted: April 15, 2010
Application Number:
20100095264
One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layout, the wafer can include topography variations which were caused by previous exposure-and-development steps. The process model can be used to predict patterns that are created on the wafer when the wafer is exposed to a…
METHOD AND APPARATUS FOR DETERMINING AN OPTICAL THRESHOLD AND A RESIST BIAS
Granted: April 8, 2010
Application Number:
20100086196
One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The system can then determine multiple aerial-image-intensity values in proximity to the iso-focal pattern by convolving the layout with multiple optical models, wherein the multiple optical models model the photolithography process's…
Increasing Scan Compression By Using X-Chains
Granted: April 1, 2010
Application Number:
20100083199
To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified…
Verification Technique Including Deriving Invariants From Constraints
Granted: April 1, 2010
Application Number:
20100083201
A method of performing formal verification on a design for an integrated circuit can include accessing a set of constraints for the design. These constraints can be partitioned based on their variables, wherein any overlapping variables can result in the conjoining of their corresponding constraints. Binary decision diagrams (BDDs) can be generated based on such conjoining. Notably, invariants can be derived from the BDDs. These invariants can include constant, symmetric/implication,…
SYSTEM AND METHOD FOR DELIVERING SOFTWARE
Granted: April 1, 2010
Application Number:
20100083243
Some embodiments of the present invention provide a system for delivering software. During operation, the system receives selections from a user, wherein the selections specify items of software to be delivered from a master site to a user site. The system also receives priority information from the user, wherein the priority information specifies a priority for delivery for the selected items of software. Next, the system determines an order of delivery for the selected items of…
SYSTEM AND METHOD FOR VERIFYING DELIVERED SOFTWARE
Granted: April 1, 2010
Application Number:
20100083246
Some embodiments of the present invention provide a system that verifies software which was distributed from a master site to a user site. During operation, the system receives a master list from the master site at the user site, where the master list specifies items of software which could be installed on the user site. The system also generates an actual list on the user site indicating which items of software are actually installed on the user site. The system then compares the actual…
METHOD AND APPARATUS FOR REMOVING A PIPELINE BUBBLE
Granted: March 25, 2010
Application Number:
20100077184
One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register has valid data and whether the pipeline is stalled. Next, the system gates the clock signal using the clock-enable signal. The augmented pipeline can determine whether a first register contains invalid data, which is associated…
METHOD AND APPARATUS FOR WORD-LEVEL NETLIST REDUCTION AND VERIFICATION USING SAME
Granted: March 25, 2010
Application Number:
20100077366
A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are…
