TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES
Granted: January 21, 2010
Application Number:
20100017760
Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality…
ENHANCING PERFORMANCE OF A CONSTRAINT SOLVER ACROSS INDIVIDUAL PROCESSES
Granted: January 21, 2010
Application Number:
20100017352
One embodiment of the present invention provides a system that reuses information associated with a constraint solving operation for a problem domain. This system begins by receiving a constraint problem from the problem domain. Then, the system searches through a problem cache for an entry which corresponds to the canonical representation. If a corresponding entry does not exist in the problem cache, the system produces an entry in the problem cache for the canonical representation.…
Method And System for Virtual Prototyping
Granted: January 21, 2010
Application Number:
20100017185
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine…
METHOD AND APPARATUS FOR DISTINGUISHING COMBINATIONAL DESIGNS
Granted: January 21, 2010
Application Number:
20100017175
Ordinary minterm counting (OMC) and weighted minterm counting (WMC) are applied as combinational design discriminators to a pair of combinational designs D1 and D2. OMC assigns the same weight to each minterm, while WMC assigns a weight that can vary. For application of minterm counting, D1 and D2 can be converted into BDDs. The size of the BDDs can be reduced by assigning binary values to some of the input variables. If the minterm counts of D1 and are within a certain tolerance, then…
METHOD AND APPARATUS FOR DETERMINING THE EFFECT OF PROCESS VARIATIONS
Granted: January 14, 2010
Application Number:
20100011325
Embodiments of the present invention provide systems and techniques for determining the effect of process variations. During operation, the system can receive a layout which includes multiple instances of a pattern. Next, the system can correct the pattern instances using different photolithography process models which model the photolithography process at different exposure and focus conditions. Next, the corrected layout can be printed on a wafer. The system can then perform electrical…
INTEGRATED SINGLE SPICE DECK SENSITIZATION FOR GATE LEVEL TOOLS
Granted: January 7, 2010
Application Number:
20100005429
One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that…
METHOD AND APPARATUS FOR CHARACTERIZING AN INTEGRATED CIRCUIT MANUFACTURING PROCESS
Granted: January 7, 2010
Application Number:
20100005436
A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance…
Interconnect-Driven Physical Synthesis Using Persistent Virtual Routing
Granted: December 24, 2009
Application Number:
20090319977
A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one…
Minimizing Effects of Interconnect Variations in Integrated Circuit Designs
Granted: December 24, 2009
Application Number:
20090319960
Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the…
METHOD AND APPARATUS FOR EXTRACTING ASSUME PROPERTIES FROM A CONSTRAINED RANDOM TEST-BENCH
Granted: December 24, 2009
Application Number:
20090319252
One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with…
Dynamically Reconfigurable Shared Scan-In Test Architecture
Granted: December 17, 2009
Application Number:
20090313514
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
Relative Positioning of Circuit Elements in Circuit Design
Granted: December 17, 2009
Application Number:
20090313594
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.
STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS
Granted: December 17, 2009
Application Number:
20090313595
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with…
Generating Variation-Aware Library Data With Efficient Device Mismatch Characterization
Granted: December 10, 2009
Application Number:
20090306953
In a method of generating variation-aware library data for statistical static timing analysis (SSTA), a “synthetic” Gaussian variable can be used to represent all instances of one or more mismatch variations in all devices (e.g. transistors), thereby capturing the effect on at least one timing property (e.g. delay or slew). By modeling device mismatch with synthetic random variables, the variation behavior (in terms of the distribution of delay, slew, constraint, etc.) can be…
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS
Granted: December 10, 2009
Application Number:
20090307641
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution…
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS
Granted: December 10, 2009
Application Number:
20090307644
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution…
METHOD AND SYSTEM FOR POST-ROUTING LITHOGRAPHY-HOTSPOT CORRECTION OF A LAYOUT
Granted: December 3, 2009
Application Number:
20090300561
One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next,…
METHOD AND SYSTEM FOR PERFORMING SEQUENTIAL EQUIVALENCE CHECKING ON INTEGRATED CIRCUIT (IC) DESIGNS
Granted: December 3, 2009
Application Number:
20090300563
One embodiment of the present invention provides a system that performs sequential equivalence checking between integrated circuit (IC) designs. During operation, the system receives a first IC design and a second IC design. Each of the first and second IC designs includes a top design level and a bottom design level, and the bottom design levels include one or more sub-blocks within the corresponding top design levels. The system then verifies if each of the sub-blocks in the bottom…
METHOD AND APPARATUS FOR RECEIVER PULSE RESPONSE DETERMINATION
Granted: November 26, 2009
Application Number:
20090290666
A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as Dn. Symbols located in the FIFO before Dn are referred to as Dn?x. Symbols located in the FIFO after Dn are referred to as Dn+x.…
METHOD AND APPARATUS FOR MODELING LONG RANGE EUVL FLARE
Granted: November 26, 2009
Application Number:
20090292508
One embodiment of the present invention provides techniques and systems for modeling long-range extreme ultraviolet lithography (EUVL) flare. During operation, the system may receive an evaluation point in a layout. Next, the system may receive an EUVL model which includes kernels that are discretized at different sampling rates, and which have different sized ambits. Specifically, a kernel that is discretized using a low sampling rate may have a longer range than a kernel that is…
