METHOD AND APPARATUS FOR USING A DATABASE TO QUICKLY IDENTIFY AND CORRECT A MANUFACTURING PROBLEM AREA IN A LAYOUT
Granted: November 19, 2009
Application Number:
20090288047
One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first…
ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE
Granted: November 19, 2009
Application Number:
20090288048
Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account…
Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array
Granted: November 19, 2009
Application Number:
20090288049
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations…
Design-For-Test-Aware Hierarchical Design Planning
Granted: November 19, 2009
Application Number:
20090288045
Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a…
HYBRID TIME AND FREQUENCY SOLUTION FOR PLL SUB-BLOCK SIMULATION
Granted: November 5, 2009
Application Number:
20090276195
A system for a fast method to simulate phase lock loop (PLL) sub-block simulation is presented. The simulation of the sub-blocks of the PLL involve solving a system of non-linear equations for the voltages and currents in the sub-blocks of the PLL. A harmonic balance method is used to solve the system of non-linear equation. The harmonic balance method involves creating a system of linear equations which is solved using a novel hybrid time and frequency domain preconditioner. The hybrid…
METHOD AND APPARATUS FOR EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION
Granted: November 5, 2009
Application Number:
20090276738
One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a…
METHOD AND APPARATUS FOR COMPUTING A DETAILED ROUTABILITY ESTIMATION
Granted: October 29, 2009
Application Number:
20090271754
One embodiment of the present invention provides a system that computes a routability estimation across a collection of local routing regions associated with a circuit layout. This system first selects a first local routing region associated with a route overflow, wherein a respective local routing region is associated with an estimation of a number of route overflows for routing layers in a region of the circuit layout. Furthermore, a respective routing layer is associated with a…
PATTERN-CLIP-BASED HOTSPOT DATABASE SYSTEM FOR LAYOUT VERIFICATION
Granted: October 29, 2009
Application Number:
20090271749
One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries in proximity to each other. Next, for each pattern clip, the system perturbs the pattern clip to determine a first range of variations…
METHOD AND APPARATUS FOR SIMULATING BEHAVIORAL CONSTRUCTS USING INDETERMINATE VALUES
Granted: October 29, 2009
Application Number:
20090271748
One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an…
Dynamically Reconfigurable Shared Scan-In Test Architecture
Granted: October 29, 2009
Application Number:
20090271673
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
DUAL-PURPOSE PERTURBATION ENGINE FOR AUTOMATICALLY PROCESSING PATTERN-CLIP-BASED MANUFACTURING HOTSPOTS
Granted: October 29, 2009
Application Number:
20090268958
One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing…
SYSTEM AND METHOD OF EQUALIZATION OF HIGH SPEED SIGNALS
Granted: October 22, 2009
Application Number:
20090262797
In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to…
MODELING A SECTOR-POLARIZED-ILLUMINATION SOURCE IN AN OPTICAL LITHOGRAPHY SYSTEM
Granted: October 22, 2009
Application Number:
20090265148
One embodiment of the present invention provides a system that constructs a source polarization model to simulate a piecewise-constant-linear polarization-configuration of an illumination source in an optical lithography system. During operation, the system starts by partitioning an illumination pupil plane of the illumination source into a set of sectors to match a physical implementation of the illumination source. Next, the system constructs the source polarization model for the…
COMPACT CIRCUIT-SIMULATION OUTPUT
Granted: October 8, 2009
Application Number:
20090254331
Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in a file, where the primary signals are independent of gate outputs in the portion of the circuit, and the secondary signals are driven by gates in the portion of the circuit. Moreover, during a second mode of the…
System And Method Of Providing Mask Defect Printability Analysis
Granted: October 1, 2009
Application Number:
20090245621
A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information…
Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects
Granted: October 1, 2009
Application Number:
20090249266
Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias.…
CONSTRAINED RANDOM SIMULATION COVERAGE CLOSURE GUIDED BY A COVER PROPERTY
Granted: October 1, 2009
Application Number:
20090249267
One embodiment of the present invention provides a system which verifies a circuit design by biasing input stimuli for the circuit design to satisfy one or more temporal coverage properties to be verified for the circuit design. This system performs a simulation in which random input stimuli are applied to the circuit design. The system performs the simulation by using a finite state automaton (FSA) instance for a temporal coverage property to observe inputs and outputs of the circuit,…
METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY
Granted: September 24, 2009
Application Number:
20090236673
A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout
METHOD AND APPARATUS FOR DETECTING NON-UNIFORM FRACTURING OF A PHOTOMASK SHAPE
Granted: September 24, 2009
Application Number:
20090238467
One embodiment of the present invention provides a system that detects an occurrence of a given shape which has been fractured into a configuration of primitive shapes which is different from a desired configuration. The system selects a fractured-shape instantiation of the given shape, to which other fractured-shape instantiations for the given shape are compared. As a part of the comparison process, the system generates a filtered mask-pattern-description which includes primitive…
SLACK-BASED TRANSITION-FAULT TESTING
Granted: September 17, 2009
Application Number:
20090235133
A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a…
