METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN
Granted: September 10, 2009
Application Number:
20090228852
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
Using a serial profiler to estimate the performance of a parallel circuit simulation
Granted: August 27, 2009
Application Number:
20090216515
Some embodiments of the present invention provide a system that profiles a serial simulation of a circuit to estimate the performance of a parallel simulation of the circuit. During operation, the system profiles execution of module instances during a serial simulation of the circuit, wherein each module instance includes code which simulates signal propagation through a corresponding circuit module. Next, the system uses execution times for the module instances obtained from the serial…
METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS FOR CIRCUIT SIMULATION
Granted: August 27, 2009
Application Number:
20090217217
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same…
Segmentation And Interpolation Of Current Waveforms
Granted: August 20, 2009
Application Number:
20090210204
A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for…
Method and Apparatus for Automatic Orientation Optimization
Granted: August 6, 2009
Application Number:
20090199142
Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology.
Hierarchical Compression For Metal One Logic Layer
Granted: July 23, 2009
Application Number:
20090187871
A method of increasing hierarchy compression of a metal 1 standard cell layout during optical proximity correction (OPC) is provided. This method can use a context determination defined from the outermost OPC correctable-edge boundaries of a metal 1 standard cell and not extending past outermost OPC correctable edge boundaries of adjacent metal 1 standard cells in other rows. The method can also include (or can alternatively include) adjusting the landing pads (resulting from metal 2…
Integrated Circuit On Corrugated Substrate
Granted: July 16, 2009
Application Number:
20090181477
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not…
VARIABLE-IMPEDANCE GATED DECOUPLING CELL
Granted: June 18, 2009
Application Number:
20090153239
Embodiments of the present invention provide a system that controls noise in a power system that includes a power rail and a ground rail. The system includes a MOS transistor coupled in series with a decoupling capacitor between the power rail and the ground rail and an inductive packaging connection coupled to the power rail in parallel with the MOS transistor and the decoupling capacitor. The combination of MOS transistor, decoupling capacitor, and inductive packaging connection form a…
METHOD AND APPARATUS FOR IDENTIFYING AND CORRECTING PHASE CONFLICTS
Granted: June 11, 2009
Application Number:
20090150850
One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the…
Correcting 3D Effects In Phase Shifting Masks Using Sub-Resolution Features
Granted: May 28, 2009
Application Number:
20090136857
Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically,…
Nonlinear Driver Model For Multi-Driver Systems
Granted: May 14, 2009
Application Number:
20090125851
A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate…
Handling Of Flat Data For Phase Processing Including Growing Shapes Within Bins To Identify Clusters
Granted: May 14, 2009
Application Number:
20090125867
Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an…
Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed Etch
Granted: May 7, 2009
Application Number:
20090114953
A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the…
Method for Trapping Implant Damage in a Semiconductor Substrate
Granted: April 30, 2009
Application Number:
20090108408
A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap…
Optimization of Post-Layout Arrays of Cells for Accelerated Transistor Level Simulation
Granted: April 30, 2009
Application Number:
20090113356
A method for optimizing post-layout array for accelerated transistor level simulation is provided. In some embodiments of the present invention, a post-layout array of cells having a plurality array lines is optimized by forming array line models for the array lines of the post-layout array of cells. Ideal sub-arrays are formed with the cells of the post-layout array. The ideal sub-array can be simulated using conventional techniques such as HAR or SOFA. Furthermore, some embodiments of…
FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM
Granted: April 30, 2009
Application Number:
20090113368
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an…
DESIGN AUTOMATION METHOD AND SYSTEM FOR ASSESSING TIMING BASED ON GAUSSIAN SLACK
Granted: April 23, 2009
Application Number:
20090106722
An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed…
METHOD AND APPARATUS FOR COMPUTING DUMMY FEATURE DENSITY FOR CHEMICAL-MECHANICAL POLISHING
Granted: April 23, 2009
Application Number:
20090106725
One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a…
METHOD AND APPARATUS FOR PERFORMING DUMMY-FILL BY USING A SET OF DUMMY-FILL CELLS
Granted: April 2, 2009
Application Number:
20090089732
An embodiment performs dummy fill in a design layout to achieve a target density that is within a narrow range of target densities. During operation, the system can receive a design layout that includes a region whose density is not within a desired range of target densities. Next, the system can receive a set of dummy-fill cells which can be used to place a dummy-fill array to fill an arbitrarily sized rectangle. The set of dummy-fill cells may contain assist features and optical…
FACILITATING PROCESS MODEL ACCURACY BY MODELING MASK CORNER ROUNDING EFFECTS
Granted: April 2, 2009
Application Number:
20090089736
An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then modify the mask…
