Method and Apparatus for Synthesis of Augmented Multimode Compactors
Granted: March 26, 2009
Application Number:
20090083597
Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.
METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR
Granted: March 26, 2009
Application Number:
20090083688
A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape…
FLASH-BASED ANTI-ALIASING TECHNIQUES FOR HIGH-ACCURACY HIGH EFFICIENCY MASK SYNTHESIS
Granted: March 26, 2009
Application Number:
20090083692
One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then…
FLASH-BASED UPDATING TECHNIQUES FOR HIGH-ACCURACY HIGH EFFICIENCY MASK SYNTHESIS
Granted: March 26, 2009
Application Number:
20090083693
Another embodiment of the present invention provides a system that computes the effect of perturbations to an input pattern layout during an OPC (Optical Proximity Correction) process. During operation, the system receives a pattern layout. The system further receives a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. Next, the system computes a model flash lookup…
Method and Apparatus for Synthesis of Augmented Multimode Compactors
Granted: March 26, 2009
Application Number:
20090083596
Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.
MODELING AN ARBITRARILY POLARIZED ILLUMINATION SOURCE IN AN OPTICAL LITHOGRAPHY SYSTEM
Granted: March 12, 2009
Application Number:
20090070083
One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the…
Identifying And Improving Robust Designs Using Statistical Timing Anaysis
Granted: March 12, 2009
Application Number:
20090070714
Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a robust circuit can be defined based on a set of criteria, which can include worst negative slack, endpoint slack distribution, timing constraint violations, and…
METHOD AND APPARATUS FOR MODELING A VECTORIAL POLARIZATION EFFECT IN AN OPTICAL LITHOGRAPHY SYSTEM
Granted: March 12, 2009
Application Number:
20090070730
One embodiment of the present invention provides a system that accurately models polarization effects in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a polarization-description grid map for a lens pupil in the optical lithography system. The system then constructs a pupil-polarization model by defining a vectorial matrix at each grid point in the grid map, wherein the vectorial matrix specifies a pupil-induced…
METHOD AND APPARATUS FOR PLACING AN INTEGRATED CIRCUIT DEVICE WITHIN AN INTEGRATED CIRCUIT LAYOUT
Granted: March 5, 2009
Application Number:
20090064072
A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation…
Approximating Wafer Intensity Change To Provide Fast Mask Defect Scoring
Granted: February 19, 2009
Application Number:
20090046920
To provide fast mask defect scoring, approximated wafer simulations (e.g. using one convolution) are performed on the defect inspection image and its corresponding reference inspection image. Using the approximated defect wafer image and the approximated reference wafer image generated by these approximated wafer simulations, a defect maximum intensity difference (MID) is computed by subtracting one approximated wafer image from the other approximated wafer image to generate a difference…
Negative Differential Resistance Pull Up Element For DRAM
Granted: February 12, 2009
Application Number:
20090039438
A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the…
Reconstructing Transaction Order Using Clump Tags
Granted: February 12, 2009
Application Number:
20090043940
A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding the transaction to avoid violations of the ordering rules.
POWER AND GROUND SHIELD MESH TO REMOVE BOTH CAPACITIVE AND INDUCTIVE SIGNAL COUPLING EFFECTS OF ROUTING IN INTEGRATED CIRCUIT DEVICE
Granted: February 5, 2009
Application Number:
20090032846
A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving…
Automatic, Hierarchy-Independent Partitioning Method For Transistor-Level Circuit Simulation
Granted: January 29, 2009
Application Number:
20090030665
A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as…
Generating A Base Curve Database To Reduce Storage Cost
Granted: January 8, 2009
Application Number:
20090013291
An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the…
METHOD AND SYSTEM FOR ENHANCING THE YIELD IN SEMICONDUCTOR MANUFACTURING
Granted: January 1, 2009
Application Number:
20090005894
Roughly described, a manufacturing process is enhanced by using TCAD and TCAD-derived models. A TCAD simulation model of the process is developed, which predicts, in dependence upon a plurality of process input parameters, a value for a performance parameter of a product to be manufactured using the process. Estimated, predicted or desired values for a calculated subset of the parameters (including either process input parameters or product performance parameters or both), are determined…
Managing Integrated Circuit Stress Using Dummy Diffusion Regions
Granted: January 1, 2009
Application Number:
20090007043
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with…
Launch-On-Shift Support for On-Chip-Clocking
Granted: December 25, 2008
Application Number:
20080320348
A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the…
Minimizing Effects of Interconnect Variations in Integrated Circuit Designs
Granted: December 25, 2008
Application Number:
20080320428
Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the…
Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor
Granted: December 18, 2008
Application Number:
20080313513
Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.
