METHOD AND APPARATUS FOR FORMALLY CHECKING EQUIVALENCE USING EQUIVALENCE RELATIONSHIPS
Granted: September 25, 2008
Application Number:
20080235253
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence…
METHOD AND APPARATUS FOR EYE-OPENING BASED OPTIMIZATION
Granted: September 25, 2008
Application Number:
20080232520
An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the polarity for stepwise changes is reversed such that the next change is in the opposite direction. Other types of search procedures can be used. Eye opening size is the difference between the eye's upper and lower edges.…
METHOD FOR DETERMINING BEST AND WORST CASES FOR INTERCONNECTS IN TIMING ANALYSIS
Granted: September 18, 2008
Application Number:
20080228460
Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values…
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC
Granted: September 4, 2008
Application Number:
20080216028
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution…
METHOD AND APPARATUS FOR INTEGRATED CHANNEL CHARACTERIZATION
Granted: August 28, 2008
Application Number:
20080208529
A periodic broadband signal can be used to determine the S21 measurement for a channel by stimulating the channel across a spectrum of interest. The channel response to such broadband signal can be measured from undersampled data captured at the receiver. The Fourier transform of the broadband signal as received, divided by the Fourier transform of broadband signal as transmitted, constitutes the S21. A physically contiguous IC can integrate both a receiver circuit, at which S21 is to be…
METHOD AND APPARATUS FOR FORMALLY CHECKING EQUIVALENCE USING EQUIVALENCE RELATIONSHIPS
Granted: August 28, 2008
Application Number:
20080208559
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts [t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove…
FORMALLY PROVING THE FUNCTIONAL EQUIVALENCE OF PIPELINED DESIGNS CONTAINING MEMORIES
Granted: August 28, 2008
Application Number:
20080209370
One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, the system determines a correspondence between operations on the first memory system and corresponding operations on the second memory system. This…
SYSTEM AND METHOD OF EQUALIZATION OF HIGH SPEED SIGNALS
Granted: August 21, 2008
Application Number:
20080198915
In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to…
USING A SUGGESTED SOLUTION TO SPEED UP A PROCESS FOR SIMULATING AND CORRECTING AN INTEGRATED CIRCUIT LAYOUT
Granted: August 21, 2008
Application Number:
20080201127
One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial…
METHOD AND APPARATUS FOR PERFORMING TARGET-IMAGE-BASED OPTICAL PROXIMITY CORRECTION
Granted: August 21, 2008
Application Number:
20080201686
A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments,…
Exposure control for phase shifting photolithographic masks
Granted: August 7, 2008
Application Number:
20080187869
Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask…
METHOD AND APPARATUS FOR DETERMINING THE TIMING OF AN INTEGRATED CIRCUIT DESIGN
Granted: July 10, 2008
Application Number:
20080168411
A system that determines the timing of an integrated circuit (IC) design is presented. During operation, the system receives a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design. Next, the system estimates capacitances for cells within the IC design based on analytic models of the cells. The system then estimates the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein…
METHOD AND APPARATUS FOR PERFORMANCE METRIC COMPATIBLE CONTROL OF DATA TRANSMISSION SIGNALS
Granted: June 19, 2008
Application Number:
20080144742
The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission system. Several classes of example embodiments, utilizing digitally controllable voltage or current sources, are presented. The classes differ based upon such factors as coupling capacitor arrangement and use of termination…
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC
Granted: June 19, 2008
Application Number:
20080148196
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution…
Chip level scan chain planning for hierarchical design flows
Granted: June 12, 2008
Application Number:
20080141086
A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the…
Phase Abstraction For Formal Verification
Granted: June 5, 2008
Application Number:
20080134114
A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce…
Method for Modeling an HDL Design Using Symbolic Simulation
Granted: May 29, 2008
Application Number:
20080126066
A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with…
Method of Correlating Silicon Stress to Device Instance Parameters for Circuit Simulation
Granted: May 29, 2008
Application Number:
20080127005
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same…
Differential voltage defectivity monitoring circuit
Granted: May 1, 2008
Application Number:
20080099762
A circuit uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The circuit includes two stacks, whose respective outputs may be compared by a comparator, and comparator's output used to determine defectivity. In some embodiments, each stack includes a first-type device (e.g. a p-channel device) and at least two second-type devices (e.g. n-channel devices). The…
Design and Layout of Phase Shifting Photolithographic Masks
Granted: March 27, 2008
Application Number:
20080076042
A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated…
