Power network analyzer for an integrated circuit design
Granted: March 13, 2008
Application Number:
20080066026
A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on…
METHOD AND APPARATUS FOR FAST IDENTIFICATION OF HIGH STRESS REGIONS IN INTEGRATED CIRCUIT STRUCTURE
Granted: March 13, 2008
Application Number:
20080066023
Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volumetric regions corresponding to those planar regions that were found to have high 2-dimensional stress. A windowing method can be used for the 2-dimensional scan, optionally with an overlap region extending…
Method For Achieving Uniform Etch Depth Using Ion Implantation And A timed Etch
Granted: March 6, 2008
Application Number:
20080057712
A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the…
Power Network Analyzer For An Integrated Circuit Design
Granted: February 28, 2008
Application Number:
20080052649
A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on…
Nonlinear Receiver Model For Gate-Level Delay Calculation
Granted: January 31, 2008
Application Number:
20080028350
A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first…
Process For Controlling Performance Characteristics Of A Negative Differential Resistance (NDR) Device
Granted: January 24, 2008
Application Number:
20080020524
A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.
ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE
Granted: December 27, 2007
Application Number:
20070298566
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
System And Method Of Providing Mask Defect Printablity Analysis
Granted: December 20, 2007
Application Number:
20070292017
A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information…
USB 2.0 Transmitter Using Only 2.5 Volt CMOS Devices
Granted: December 6, 2007
Application Number:
20070279096
A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V to 3.3V, and a pulldown signal range of 0V to 2.5V, whereby the pullup and pulldown transistors are subjected to 2.5V gate-to-source potentials. A protection/bias circuit biases the PMOS…
Patterning A Single Integrated Circuit Layer Using Multiple Masks And Multiple Masking Layers
Granted: November 29, 2007
Application Number:
20070275309
A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask.…
Nonlinear Driver Model For Multi-Driver Systems
Granted: November 8, 2007
Application Number:
20070261010
A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate…
STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS
Granted: October 25, 2007
Application Number:
20070246776
Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel…
Dummy Filling Technique For Improved Planarization Of Chip Surface Topography
Granted: October 18, 2007
Application Number:
20070245284
The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile…
Incrementally Resolved Phase-Shift Conflicts In Layouts For Phase-Shifted Features
Granted: October 18, 2007
Application Number:
20070245291
Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be placed to define critical features, wherein the pairs of shifters conform to predetermined design rules. After placement, phase information for the shifters associated with the set of critical features can be assigned. Complex…
Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis
Granted: September 27, 2007
Application Number:
20070226668
A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews selected setup/hold time pair stored in the cell…
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
Granted: August 30, 2007
Application Number:
20070202652
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
Managing integrated circuit stress using dummy diffusion regions
Granted: August 30, 2007
Application Number:
20070202662
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with…
Managing integrated circuit stress using stress adjustment trenches
Granted: August 30, 2007
Application Number:
20070202663
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with…
Stress-managed revision of integrated circuit layouts
Granted: August 30, 2007
Application Number:
20070204250
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with…
Hierarchical Signal Integrity Analysis Using Interface Logic Models
Granted: July 19, 2007
Application Number:
20070168897
Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information for the blocks. To further increase the speed and accuracy of SI analysis, enhanced interface logic models (SI-ILMs) can be used. An…
