Logic Timing and Reliability Repair for Nanowire Circuits
Granted: January 4, 2018
Application Number:
20180005707
A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. A repair circuit can be…
Optimizing The Ordering Of The Inputs To Large Commutative-Associative Trees Of Logic Gates
Granted: January 4, 2018
Application Number:
20180004862
A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.
Integrated Circuit Devices Having Features With Reduced Edge Curvature and Methods for Manufacturing the Same
Granted: December 28, 2017
Application Number:
20170373136
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
2D Material Super Capacitors
Granted: December 28, 2017
Application Number:
20170373134
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide.…
ROBUST NEGATIVE BIT-LINE AND RELIABILITY AWARE WRITE ASSIST
Granted: December 14, 2017
Application Number:
20170358345
A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.
CONTEXT AWARE CLOCK TREE SYNTHESIS
Granted: December 14, 2017
Application Number:
20170357746
Systems and techniques are described for context aware clock tree synthesis (CTS). A probability value can be computed for each clock sink in the set of clock sinks, wherein each probability value represents a probability that the corresponding clock sink has a critical clock latency. Next, the set of clock sinks can be clustered into a set of clock sink clusters based on the probability values. An optimization goal for each clock sink cluster can be selected, and an optimized subtree…
DETERMINING THE RESISTANCE OF A CONDUCTING STRUCTURE
Granted: December 7, 2017
Application Number:
20170351803
Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. Next, a matrix equation can be constructed, wherein for at least one polygon in the set of polygons, electric potentials of boundary elements on the boundaries of the polygon are represented by linear combinations of electric potentials of two or more…
SYSTEMS AND METHODS FOR ADAPTIVE ANALYSIS OF SOFTWARE
Granted: November 16, 2017
Application Number:
20170329974
Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application; and the application architecture model comprises a plurality of component models. A property model type may be selected, based on a property to be checked, from a plurality of property model types. One or more component models may be…
SYSTEMS AND METHODS FOR ANALYZING SOFTWARE USING QUERIES
Granted: November 16, 2017
Application Number:
20170331850
Systems and methods for software verification. In some embodiments, a first statement is identified, from a discovery query written in a query language, the first statement comprising a side-effect construct with at least a first parameter and a second parameter, wherein: the first parameter of the side-effect construct comprises at least one second statement specifying one or more actions to be performed; and the second parameter of the side-effect construct comprises at least one…
Method and Apparatus for Floating or Applying Voltage to a Well of an Integrated Circuit
Granted: November 16, 2017
Application Number:
20170330872
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the…
Parameter Extraction of DFT
Granted: November 16, 2017
Application Number:
20170329882
Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.
SYSTEMS AND METHODS FOR INCREMENTAL ANALYSIS OF SOFTWARE
Granted: November 16, 2017
Application Number:
20170329693
Systems and methods for software verification. In some embodiments, a first application architecture model is generated for a software application, wherein: the first application architecture model is generated based on a first version of source code of the software application; and the first application architecture model comprises a plurality of component models. A second version of source code may be compared against the first version of source code to determine at least one…
SYSTEM AND METHODS FOR MODEL-BASED ANALYSIS OF SOFTWARE
Granted: November 16, 2017
Application Number:
20170329692
Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application and a framework model representing a software framework using which the software application is developed; and the application architecture model comprises a plurality of component models. One or more component models may be selected, based on…
SYSTEMS AND METHODS FOR USING SEMANTIC QUERIES TO ANALYZE SOFTWARE
Granted: November 16, 2017
Application Number:
20170329691
Systems and methods for software verification. In some embodiments, a statement is identified from a discovery query written in a query language, comprising a semantic operator with at least a first parameter and a second parameter, wherein: the first parameter comprises a first syntactic pattern; the second parameter comprises a second syntactic pattern; and the semantic operator represents a semantic relationship between two program elements. Source code of a software application may…
POWER HARVESTING FOR INTEGRATED CIRCUITS
Granted: October 5, 2017
Application Number:
20170287977
Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed…
CUSTOM LAYOUT OF INTEGRATED CIRCUIT (IC) DESIGNS
Granted: October 5, 2017
Application Number:
20170286584
Systems and techniques for facilitating layout of an integrated circuit (IC) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the IC design that correspond to a net. Next, the layout of the IC design can be displayed in a graphical user interface (GUI) of the IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of the device contacts so that the diffusion region is aligned with…
Method for Testing computer program product
Granted: September 28, 2017
Application Number:
20170277890
This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one signature set of binary data from a read-only section of the reference computer program library, wherein the at least one signature set of binary data is determined to…
IMAGE PROCESSING METHOD
Granted: August 31, 2017
Application Number:
20170249529
A computer-implemented image processing technique for selectively recovering the features of an original CAD model after the original CAD model has been converted to a digitized image and a new CAD model generated from the digitized image. The original boundary representation provides a template to transform the representation through processing under governance of a programmed processor so as to recover accuracy and reintroduce feature edges and feature corners as well as other detailed…
Layer Class Relative Density for Technology Modeling in IC Technology
Granted: August 10, 2017
Application Number:
20170228492
A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.
3D RESIST PROFILE AWARE RESOLUTION ENHANCEMENT TECHNIQUES
Granted: August 3, 2017
Application Number:
20170220723
Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.
