Tined Gate to Control Threshold Voltage in a Device Formed of Materials Having Piezoelectric Properties
Granted: June 29, 2017
Application Number:
20170186860
Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least…
POWER-AWARE DYNAMIC ENCODING
Granted: June 1, 2017
Application Number:
20170154132
Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression,…
TOPOGRAPHY SIMULATION OF ETCHING AND/OR DEPOSITION ON A PHYSICAL STRUCTURE
Granted: May 25, 2017
Application Number:
20170147724
Systems and techniques are described for topography simulation of etching and/or deposition on a physical structure. The structural information can be represented using a three-dimensional (3D) voxel grid data structure. For each particle emitted by a Monte-Carlo particle emission model, a topographical modification caused by the particle can be determined by (1) calculating fluxes, (2) evaluating surface reactions, and (3) modifying the physical structure. The effect of the etching…
ANNOTATING ISOLATED SIGNALS
Granted: May 25, 2017
Application Number:
20170147720
Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells in the power intent specification. The correspondence can be stored in a memory of a computer, and can be used for annotating a visual representation of a signal in a…
ATOMIC STRUCTURE OPTIMIZATION
Granted: May 4, 2017
Application Number:
20170124293
Electronic design automation modules simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.
ALTERNATIVE HIERARCHICAL VIEWS OF A CIRCUIT DESIGN
Granted: March 30, 2017
Application Number:
20170091367
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the…
METHOD TO APPROXIMATE CHEMICAL POTENTIAL IN A TERNARY OR QUATERNARY SEMICONDUCTOR
Granted: March 23, 2017
Application Number:
20170083644
Roughly described, a method is provided to approximate chemical potentials of elements in ternary and quaternary compound semiconductors, for example III-V semiconductors. In embodiments of the present invention, three, four, or more relationships are solved together to find approximated chemical potentials for each group III element and each group V element. The first relationship relates total energy of a defect-free system to the sum, over all of the group III and group V elements, of…
ACCURATE GLITCH DETECTION
Granted: February 23, 2017
Application Number:
20170053051
Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when…
IDENTIFYING FAILURE MECHANISMS BASED ON A POPULATION OF SCAN DIAGNOSTIC REPORTS
Granted: February 23, 2017
Application Number:
20170052861
Systems and techniques for identifying failure mechanisms based on a population of scan diagnostic reports is described. Given a population of scan diagnostic reports, a mixed membership model can be used for computing a topic distribution for each portion of each scan diagnostic report and a feature distribution for each topic. The failure mechanisms can be identified based on the topic distributions for the portions of the scan diagnostic reports and the feature distributions for the…
2D MATERIAL SUPER CAPACITORS
Granted: February 9, 2017
Application Number:
20170040411
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide.…
Pre-Silicon Design Rule Evaluation
Granted: February 9, 2017
Application Number:
20170039308
Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior…
Identifying Software Components in a Software Codebase
Granted: February 2, 2017
Application Number:
20170032117
Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching software files. In an embodiment, the reference database may store a…
Methods for Manufacturing Integrated Circuit Devices Having Features With Reduced Edge Curvature
Granted: January 26, 2017
Application Number:
20170025496
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall…
POWER-AND-GROUND (PG) NETWORK CHARACTERIZATION AND DISTRIBUTED PG NETWORK CREATION FOR HIERARCHICAL CIRCUIT DESIGNS
Granted: January 19, 2017
Application Number:
20170017746
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG…
METHOD AND APPARATUS FOR WORD-LEVEL NETLIST PREPROCESSING AND ANALYSIS USING SAME
Granted: January 12, 2017
Application Number:
20170011140
A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are…
SYSTEM AND METHOD FOR HIERARCHICAL POWER VERIFICATION
Granted: January 12, 2017
Application Number:
20170011138
A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include…
LOOK-AHEAD TIMING PREDICTION FOR MULTI-INSTANCE MODULE (MIM) ENGINEERING CHANGE ORDER (ECO)
Granted: January 5, 2017
Application Number:
20170004244
Some embodiments determine a merged timing graph for a multi-instance module (MIM), wherein each node in the merged timing graph corresponds to a pin in the MIM, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the MIM in a circuit design. The embodiments can then determine an ECO for the MIM based on the merged timing graph.
NETLIST ABSTRACTION FOR CIRCUIT DESIGN FLOORPLANNING
Granted: January 5, 2017
Application Number:
20170004240
Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.
METHOD AND SYSTEM FOR CHECKING AND CORRECTING SHOOT-THROUGH IN RTL SIMULATION
Granted: November 24, 2016
Application Number:
20160342727
In a method of checking an integrated circuit design prior to running a simulation, a shoot-through RTL Checker reads RTL design files, uses a simulator delta cycle definitions to compute clock delta delays, and helps to correct and report any conditions that are expected will cause the simulation to generate incorrect results, in particular shoot-through conditions at circuit memory elements such as source and destination flip-flops or registers.
MULTI-SCALE SIMULATION INCLUDING FIRST PRINCIPLES BAND STRUCTURE EXTRACTION
Granted: November 17, 2016
Application Number:
20160335381
Electronic design automation modules include a first tool and a second tool. The first tool includes ab initio simulation procedures configured to use input parameters to produce information about a band structure of a simulated material on a first simulation scale specified at least in part by the input parameters. The second tool includes a simulation procedure configured to used information about the band structure of the simulated material produced by the first tool to extract…
