Fast and scalable methodology for analog defect detectability analysis
Granted: February 14, 2023
Patent Number:
11579994
A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit…
Frame parser executing subsets of instructions in parallel for processing a frame header
Granted: February 14, 2023
Patent Number:
11579890
An integrated circuit (IC) may include a set of instruction list engines (ILEs) that execute in parallel, where each ILE stores a subset of a set of instructions for processing a header of a frame, and where each ILE generates an ILE result based on executing the subset of the set of instructions. The IC may include a circuit to determine a result of parsing the header of the frame based on merging ILE results generated by the set of ILEs.
Temperature tracked dynamic keeper implementation to enable read operations
Granted: February 7, 2023
Patent Number:
11574675
A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second…
Adaptive cell-aware test model for circuit diagnosis
Granted: February 7, 2023
Patent Number:
11573873
Systems and methods disclosed include receiving defect data from a test of a semiconductor device comprising a circuit, the circuit comprising a cell, the cell comprising a first input, a second input and an output, and modeling a first plurality of cell defect modes of the cell with a first multiple input transition cell fault model (MTCFM), the cell defect modes associated with a first signal transition on the first input, and a second signal transition on the second input or the…
Duty cycle adjustment circuit with independent range and step size control
Granted: January 31, 2023
Patent Number:
11569806
Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter…
Discovering contextualized placeholder variables in template code
Granted: January 31, 2023
Patent Number:
11568130
Disclosed herein are computer-implemented method, system, and computer-program product (computer-readable storage medium) embodiments for discovering contextualized placeholder variables in template code. Some embodiments include invoking a render call to a template engine to render an input template and then receiving a message identifying a placeholder variable within the input template in response to invoking the render call. These embodiments may further include generating multiple…
Mask rule checking for curvilinear masks for electronic circuits
Granted: January 31, 2023
Patent Number:
11568127
A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two…
Generating simulation-friendly compact physical models for passive structures
Granted: January 31, 2023
Patent Number:
11568117
A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes…
Correlation between emission spots utilizing CAD data in combination with emission microscope images
Granted: January 24, 2023
Patent Number:
11561256
A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of…
Correlation between emission spots utilizing CAD data in combination with emission microscope images
Granted: January 24, 2023
Patent Number:
11561256
A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of…
Layout of photonic integrated circuits using fixed coordinate grids
Granted: January 17, 2023
Patent Number:
11556689
Embodiments relate to the layout of photonic integrated circuits using fixed coordinate grids. In some embodiments, a method includes receiving a request to place a first photonic component within a layout of a photonic integrated circuit. Positionings of components within the layout are represented in a design database utilizing a grid with fixed coordinates. The method further includes calculating, by a processor, precise coordinates and snapped coordinates for positioning of the first…
Scalable formal security verification of circuit designs
Granted: January 17, 2023
Patent Number:
11556676
A security verification system performs security verification of a circuit design. The security verification system simplifies formal security verification of the circuit design by replacing circuit blocks of the circuit with black box circuit blocks. The security verification system instruments the circuit design so that black-boxing can be performed for security verification without changing the security decision over the data paths. The security verification system uses dependence…
Automatic root cause analysis of complex static violations by static information repository exploration
Granted: January 17, 2023
Patent Number:
11556406
The independent claims of this patent signify a concise description of embodiments. An automatic process for determining and/or predicting the original root-cause(s) of a violation is proposed using two major enhancements on top of the current VC-Static solution. First, an information repository is created by mining various Static checker components' analysis information, and second, an analysis framework is created which systematically prunes the above-mentioned information repository…
Using mask fabrication models in correction of lithographic masks
Granted: January 17, 2023
Patent Number:
11556052
A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from…
Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements
Granted: January 10, 2023
Patent Number:
11550979
A system enhances a system design to incorporate safety measures. The system receives a system design for processing through various stages of design using design tools, for example electronic design automation tools for introducing safety features in a circuit design. The system receives safety requirements for the system design, the safety requirements specifying safety measures for the system design. The system generates from the safety requirements, a safety specification storing a…
On-the-fly computation of analog mixed-signal (AMS) measurements
Granted: January 3, 2023
Patent Number:
11544435
The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more…
Timing and placement co-optimization for engineering change order (ECO) cells
Granted: December 27, 2022
Patent Number:
11537775
A system and method for providing timing and placement co-optimization for engineering change order (ECO) cells is described. According to one embodiment, an ECO for a current design of an integrated circuit is accessed. The ECO includes inserting an ECO cell among placed and routed current cells of the current design. A target region in the current design is identified for placement of the ECO cell, but the target region has insufficient open space to place the ECO cell. At least one…
Enhanced read sensing margin for SRAM cell arrays
Granted: December 20, 2022
Patent Number:
11532352
This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the…
Vector generation for maximum instantaneous peak power
Granted: December 20, 2022
Patent Number:
11531797
A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating…
Clock network power estimation for logical designs
Granted: December 13, 2022
Patent Number:
11526642
An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a…
