Input Schmitt buffer operating at a high voltage using low voltage devices
Granted: April 4, 2023
Patent Number:
11621704
An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.
Pattern based die connector assignment using machine learning image recognition
Granted: April 4, 2023
Patent Number:
11620427
A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical…
Transistor—level defect coverage and defect simulation
Granted: April 4, 2023
Patent Number:
11620424
A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the…
Logic simulation of circuit designs using on-the-fly bit reduction for constraint solving
Granted: March 28, 2023
Patent Number:
11615225
A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on…
Systems and methods of intelligent and directed dynamic application security testing
Granted: March 7, 2023
Patent Number:
11601462
Disclosed are systems, methods and computer readable mediums for intelligent and directed dynamic application security testing. The systems, methods and computer-readable mediums can be configured to receive an attack location and an attack type for a web-application, transmit the attack location and attack type to a ID-DAST platform, receive from the ID-DAST platform a payload, attack the web-application using the payload, and receive results of the attack.
Internet of things (IoT) power and performance management technique and circuit methodology
Granted: March 7, 2023
Patent Number:
11599185
Energy consumption is reduced within an Internet of Things (IoT) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (VDDa) used to supply the internal circuitry is reduced from a VDD supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. The first internal supply voltage (VDDa) may be reduced to a voltage that is one threshold voltage (Vtp) lower than the…
Self-adjustable self-timed dual-rail SRAM
Granted: February 28, 2023
Patent Number:
11594276
A dual-rail memory includes, in part, a memory array that operates using a first supply voltage, and a periphery circuit that operates using a second supply voltage. The periphery circuit includes, in part, a clock generation circuit and a comparator. The dual-rail memory also includes a level shifter that varies the voltage level of a number of signals of the memory between the first and second supply voltages. The clock generation circuit is adapted, among other operations, to generate…
Glitch power analysis with register transfer level vectors
Granted: February 28, 2023
Patent Number:
11593543
A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.
Keep-through regions for handling end-of-line rules in routing
Granted: February 21, 2023
Patent Number:
11586796
A routing process applied to design integrated circuits uses keep-through regions. Keep-through regions specify areas which metal shapes may overlap but where metal shapes may not have line ends. The keep-through regions are generated based on end-of-line rules applicable to routing of the design. These keep-through regions are then used in determining the layout of interconnects for the design. The interconnects are composed of metal shapes, and the line ends of the metal shapes are…
Fast and scalable methodology for analog defect detectability analysis
Granted: February 14, 2023
Patent Number:
11579994
A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit…
Frame parser executing subsets of instructions in parallel for processing a frame header
Granted: February 14, 2023
Patent Number:
11579890
An integrated circuit (IC) may include a set of instruction list engines (ILEs) that execute in parallel, where each ILE stores a subset of a set of instructions for processing a header of a frame, and where each ILE generates an ILE result based on executing the subset of the set of instructions. The IC may include a circuit to determine a result of parsing the header of the frame based on merging ILE results generated by the set of ILEs.
Temperature tracked dynamic keeper implementation to enable read operations
Granted: February 7, 2023
Patent Number:
11574675
A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second…
Adaptive cell-aware test model for circuit diagnosis
Granted: February 7, 2023
Patent Number:
11573873
Systems and methods disclosed include receiving defect data from a test of a semiconductor device comprising a circuit, the circuit comprising a cell, the cell comprising a first input, a second input and an output, and modeling a first plurality of cell defect modes of the cell with a first multiple input transition cell fault model (MTCFM), the cell defect modes associated with a first signal transition on the first input, and a second signal transition on the second input or the…
Duty cycle adjustment circuit with independent range and step size control
Granted: January 31, 2023
Patent Number:
11569806
Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter…
Discovering contextualized placeholder variables in template code
Granted: January 31, 2023
Patent Number:
11568130
Disclosed herein are computer-implemented method, system, and computer-program product (computer-readable storage medium) embodiments for discovering contextualized placeholder variables in template code. Some embodiments include invoking a render call to a template engine to render an input template and then receiving a message identifying a placeholder variable within the input template in response to invoking the render call. These embodiments may further include generating multiple…
Mask rule checking for curvilinear masks for electronic circuits
Granted: January 31, 2023
Patent Number:
11568127
A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two…
Generating simulation-friendly compact physical models for passive structures
Granted: January 31, 2023
Patent Number:
11568117
A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes…
Correlation between emission spots utilizing CAD data in combination with emission microscope images
Granted: January 24, 2023
Patent Number:
11561256
A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of…
Correlation between emission spots utilizing CAD data in combination with emission microscope images
Granted: January 24, 2023
Patent Number:
11561256
A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of…
Automatic root cause analysis of complex static violations by static information repository exploration
Granted: January 17, 2023
Patent Number:
11556406
The independent claims of this patent signify a concise description of embodiments. An automatic process for determining and/or predicting the original root-cause(s) of a violation is proposed using two major enhancements on top of the current VC-Static solution. First, an information repository is created by mining various Static checker components' analysis information, and second, an analysis framework is created which systematically prunes the above-mentioned information repository…
