Construction, modeling, and mapping of multi-output cells
Granted: May 23, 2023
Patent Number:
11657205
A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second…
Independent skew control of a multi-phase clock
Granted: May 16, 2023
Patent Number:
11652475
A circuit includes, in part, a first transistor receiving a first clock signal at its gate, a second transistor receiving a second clock signal at its gate, a first impedance coupled to the drain terminal of the first transistor, a second impedance coupled to the drain terminal of the second transistor, a current source coupled to the source terminals of the first and second transistors, a third transistor receiving a third clock signal at its gate, a fourth transistor receiving a fourth…
Low latency decoder for error correcting codes
Granted: May 16, 2023
Patent Number:
11651830
A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The…
Dose optimization techniques for mask synthesis tools
Granted: May 16, 2023
Patent Number:
11651135
A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.
Glitch source identification and ranking
Granted: May 16, 2023
Patent Number:
11651131
Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch…
Selecting a subset of training data from a data pool for a power prediction model
Granted: May 16, 2023
Patent Number:
11651129
A method includes generating a plurality of vector sequences based on input signals of an electric circuit design and encoding the plurality of vector sequences. The method also includes clustering the plurality of encoded vector sequences into a plurality of clusters and selecting a set of encoded vector sequences from the plurality of clusters. The method further includes selecting a first set of vector sequences corresponding to the selected set of encoded vector sequences, selecting…
Inverse etch model for mask synthesis
Granted: May 9, 2023
Patent Number:
11644746
A first set of critical dimension (CD) measurements of resist patterns created by a lithography process and a second set of CD measurements of water patterns created by an etch process may be obtained. A forward etch model and an inverse etch model may be calibrated together by reducing (1) a first prediction error between the second set of CD measurements and a first set of simulated CDs predicted by the forward etch model based on the resist patterns, a second prediction error between…
Obtaining a mask using a cost function gradient from a jacobian matrix generated from a perturbation look-up table
Granted: May 9, 2023
Patent Number:
11644747
Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask…
Inverse etch model for mask synthesis
Granted: May 9, 2023
Patent Number:
11644746
A first set of critical dimension (CD) measurements of resist patterns created by a lithography process and a second set of CD measurements of water patterns created by an etch process may be obtained. A forward etch model and an inverse etch model may be calibrated together by reducing (1) a first prediction error between the second set of CD measurements and a first set of simulated CDs predicted by the forward etch model based on the resist patterns, a second prediction error between…
Obtaining a mask using a cost function gradient from a jacobian matrix generated from a perturbation look-up table
Granted: May 9, 2023
Patent Number:
11644747
Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask…
Asynchronous chip-to-chip communication
Granted: May 2, 2023
Patent Number:
11641268
Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the…
Single flux quantum inverter circuit
Granted: May 2, 2023
Patent Number:
11641194
A circuit can include a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit can store a reset state or a set state, and can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using a JJ-based current source. The second sub-circuit can switch the first sub-circuit to the set state in response to receiving a pulse. The third…
Source mask optimization by process defects prediction
Granted: May 2, 2023
Patent Number:
11640490
A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a defect rate in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to…
Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes
Granted: April 25, 2023
Patent Number:
11636388
A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML…
Performance tuning of a hardware description language simulator
Granted: April 25, 2023
Patent Number:
11636244
Some aspects of this disclosure are directed automated performance tuning of a hardware description language (HDL) simulation system. For example, some aspects of this disclosure relate to a method, including generating, by a first subsystem optimizer, a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system. The plurality of recommendations are generated by the first subsystem optimizer using one or more optimization…
Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure
Granted: April 18, 2023
Patent Number:
11630934
Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application…
Packetized power-on-self-test controller for built-in self-test
Granted: April 11, 2023
Patent Number:
11626178
Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.
Transistor—level defect coverage and defect simulation
Granted: April 4, 2023
Patent Number:
11620424
A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the…
Input Schmitt buffer operating at a high voltage using low voltage devices
Granted: April 4, 2023
Patent Number:
11621704
An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.
Pattern based die connector assignment using machine learning image recognition
Granted: April 4, 2023
Patent Number:
11620427
A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical…
