Power estimation system
Granted: November 8, 2022
Patent Number:
11493971
A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.
Robotic systems and corresponding methods for engaging server back-plane connectors
Granted: November 8, 2022
Patent Number:
11491648
A linear motion actuation system and method of using the same may be utilized for installing or removing a server blade within a server rack, via a linear motion assembly fastened to a server blade and configured for linear motion with the server blade; a bracket fastened to a server rack; and at least one linear motion actuator comprising: a first component secured with the linear motion assembly; and a second component movably secured with the first component and secured with the…
Josephson junction structures
Granted: November 1, 2022
Patent Number:
11489102
Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a first superconducting structure and a second superconducting structure disposed on a plane parallel to a silicon wafer surface. A non-superconducting structure may be disposed between the first superconducting structure and the second superconducting structure. A direction of current flow through the non-superconducting structure may be parallel to the silicon wafer surface.
Pattern matching using anchors during integrated circuit verification
Granted: November 1, 2022
Patent Number:
11487930
Pattern matching using anchors during integrated circuit (IC) verification is disclosed. According to one embodiment, a method includes obtaining match time estimates associated with pattern anchors of different anchor types for an IC pattern, generating revised match time estimates based on a target IC layout, and then selecting the pattern anchor associated with the shortest revised match time estimate. Then, target anchors of the same anchor type as the selected pattern anchor are…
Learning-based toggle estimation
Granted: October 18, 2022
Patent Number:
11475293
A method of estimating a toggle count of a circuit, includes, in part, simulating the circuit to generate training data and an associated training toggle count of the internal nodes of the circuit in response to a test bench, training a neural network system to generate an estimate of the training toggle count in accordance with the training data and the associated training toggle count, simulating the circuit to generate simulation data in response to a first set of input values applied…
Inclusion of stochastic behavior in source mask optimization
Granted: October 18, 2022
Patent Number:
11475201
A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a…
Hardware simulation systems and methods for identifying state-holding loops and oscillating loops
Granted: October 18, 2022
Patent Number:
11475197
A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least…
Information theoretic subgraph caching
Granted: October 11, 2022
Patent Number:
11468218
Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be…
Circuit for improving edge-rates in voltage-mode transmitters
Granted: October 11, 2022
Patent Number:
11469741
The driver circuit includes a pull-up network having a first pull-up transistor controlled by a data signal, a second pull-up transistor coupled between the first pull-up transistor and a first power supply voltage, and a third pull-up transistor coupled in parallel with the second pull-up transistor. The third pull-up transistor is configured to turn on for at least one clock cycle responsive to a change in the logic level of the data signal being detected.
Stochastic signal prediction in compact modeling
Granted: October 11, 2022
Patent Number:
11468222
A method, includes, in part, defining a continuous signal, defining a threshold value, calibrating the continuous signal and the threshold value from measurements made on edges of one or more patterns on a mask and corresponding edges of the patterns on a wafer, convolving the continuous signal with a kernel to form a corrected signal, and establishing, by a processor, a probability of forming an edge at a point along the corrected signal in accordance with a difference between the value…
Machine learning (ML)-based static verification for derived hardware-design elements
Granted: October 11, 2022
Patent Number:
11467851
Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the…
Glitch analysis and glitch power estimation system
Granted: October 4, 2022
Patent Number:
11461523
A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.
Method to perform secondary-PG aware buffering in IC design flow
Granted: September 20, 2022
Patent Number:
11449660
A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary…
Lithography-based pattern optimization
Granted: September 20, 2022
Patent Number:
11449659
An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is…
Defect weight formulas for analog defect simulation
Granted: September 13, 2022
Patent Number:
11443092
A method, apparatus, and/or computer program product can perform an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter.…
System and method for power analysis for design logic circuit with irregular clock
Granted: September 13, 2022
Patent Number:
11443087
A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design…
Parallel plate capacitor resistance modeling and extraction
Granted: May 10, 2022
Patent Number:
11328873
A parallel plate capacitor structure in an integrated circuit has a first plate and a second plate separated by an insulator, such as a dielectric. Both plates are connected to an interconnect structure at a plurality of connection points. The area of the first plate that overlaps with the second plate is identified. This overlap region does not include any connection points on the first plate. For this overlap region, the lumped element model for the first plate includes nodes on the…
Refining multi-bit flip flops mapping without explicit de-banking and re-banking
Granted: May 10, 2022
Patent Number:
11328109
Refining multi-bit flip flops mapping without explicit de-banking and re-banking is provided by identifying a set of equivalent flops in a layout, that include a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; and remapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the…
Event-level parallel simulation using dynamic synchronization
Granted: May 10, 2022
Patent Number:
11327790
The independent claims of this patent signify a concise description of embodiments. A method is provided for parallel simulation using synchronization during simulation. The method comprises executing a plurality of threads in parallel, identifying a first event block and a second event block of a circuit design, calculating a minimum delay (minDelay) based on a current simulation time, scheduled times for execution of the first event block and the second event block, and causal delays…
Lithography improvement based on defect probability distributions and critical dimension variations
Granted: April 26, 2022
Patent Number:
11314171
Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of…
