Lithography improvement based on defect probability distributions and critical dimension variations
Granted: April 26, 2022
Patent Number:
11314171
Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of…
Partitioning in post-layout circuit simulation
Granted: April 19, 2022
Patent Number:
11308253
The independent claims of this patent signify a concise description of embodiments. New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the…
Area efficient and high-performance wordline segmented architecture
Granted: April 12, 2022
Patent Number:
11302365
A memory array including a plurality of memory cells and a plurality of drivers is disclosed. The plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. Memory cells corresponding to a row of the plurality of rows may be logically grouped into a plurality of memory array segments. The plurality of drivers may be coupled to corresponding first ends of corresponding memory array segments of the plurality of memory array segments. Second ends of the…
Feasibility analysis of engineering change orders
Granted: April 12, 2022
Patent Number:
11301614
An existing design of an integrated circuit includes existing cells that have already been placed and routed. An engineering change order (ECO) specifies additional new cells (ECO cells) to be inserted into the existing design. The ECO cells are also associated with target locations for their placement among the existing cells, but these target locations may violate design rules. The feasibility of “legalizing” the placement of the ECO cells within the existing design is assessed as…
Save and restore register
Granted: April 12, 2022
Patent Number:
11300614
A save and restore (SR) register system is disclosed. Some embodiments include a first memory state element (MSE), a second MSE, and a control circuit. The first MSE is configured to: clock in a first data value during a normal mode and hold the first data value during a first testing mode; and clock in a first test sequence during a second testing mode. The second MSE is configured to: clock in the first data value during the normal mode; and clock in a second test sequence during the…
Time correlation in hybrid emulation system
Granted: April 5, 2022
Patent Number:
11295052
A hybrid emulation system includes a hardware emulation system, a simulation system, and a co-simulation interface. The hardware emulation system emulates a first portion of a design under test (DUT) during a hybrid emulation. The emulation runs in a first time domain local to the hardware emulation system. The simulation system simulates a second portion of the DUT during the hybrid emulation. The simulation runs in a second time domain local to the simulation system. The first time…
Integrated circuit design modification for localization of scan chain defects
Granted: March 29, 2022
Patent Number:
11288428
An integrated circuit (IC) design comprising a scan chain may be received, where stimulus values may be scanned-in and response values may be scanned-out through a scan path in the scan chain, where the scan path may include a first scan cell and a second scan cell such that the first scan cell is downstream with respect to the second scan cell. The scan chain may be modified to enable observation of a 0 and a 1 value in the first scan cell in presence of a defect in the second scan…
Automated root-cause analysis, visualization, and debugging of static verification results
Granted: March 29, 2022
Patent Number:
11288427
Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug…
Analyzing delay variations and transition time variations for electronic circuits
Granted: March 29, 2022
Patent Number:
11288426
A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing…
Hardware simulation systems and methods for reducing signal dumping time and size by fast dynamical partial aliasing of signals having similar waveform
Granted: March 15, 2022
Patent Number:
11275877
Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second…
Crystal orientation engineering to achieve consistent nanowire shapes
Granted: March 1, 2022
Patent Number:
11264458
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a…
Machine-learning driven prediction in integrated circuit design
Granted: February 22, 2022
Patent Number:
11256845
Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.
Efficient calculation of ED25519/448 signature verification in an encryption device
Granted: February 15, 2022
Patent Number:
11251973
A computer system module(s) substitutes a double scalar multiplication, used for signature verification in an encryption/decryption system, for two single scalar multiplications. The modules verify a group equation defined by [S]B=R+[k]A? of the encryption/decryption system, where S is an integer characterized by the signature, K is an integer generated by a message being encrypted, B is a base point on the elliptic curve, R is a point on the elliptic curve and characterized by the…
Adaptive parallelization for multi-scale simulation
Granted: February 15, 2022
Patent Number:
11249813
Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result…
Verifying glitches in reset path using formal verification and simulation
Granted: February 1, 2022
Patent Number:
11238202
A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the…
Layout-aware test pattern generation and fault detection
Granted: February 1, 2022
Patent Number:
11237210
Methods and apparatuses to assign faults to nets in an integrated circuit (IC) are described. Each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins. During operation, a fan-out structure of a net can be partitioned into a set of non-overlapping subnets and a set of branch nodes, wherein each branch node electrically couples three or more non-overlapping subnets. Next, each branch node can be represented…
Single flux quantum circuit that includes a sequencing circuit
Granted: January 25, 2022
Patent Number:
11233516
A single flux quantum (SFQ) circuit can include a combinational logic network, which can include a set of SFQ logic cells. The SFQ circuit can also include an SFQ sequencing circuit, which can be used to generate delayed versions of clock pulses to clock the set of SFQ logic cells.
SAT solver based on interpretation and truth table analysis
Granted: January 25, 2022
Patent Number:
11232174
Techniques and systems for solving Boolean satisfiability (SAT) problems are described. Some embodiments solve SAT problems using efficient construction of truth tables. Some embodiments can improve performance of SAT solvers by using truth tables instead of incurring the overhead of Conjunctive Normal Form (CNF) conversion.
Augmenting an integrated circuit (IC) design simulation model to improve performance during verification
Granted: January 25, 2022
Patent Number:
11231462
An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can…
State table complexity reduction in a hierarchical verification flow
Granted: January 11, 2022
Patent Number:
11222154
State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical…
