Hardware simulation systems and methods for reducing signal dumping time and size by fast dynamical partial aliasing of signals having similar waveform
Granted: March 15, 2022
Patent Number:
11275877
Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second…
Crystal orientation engineering to achieve consistent nanowire shapes
Granted: March 1, 2022
Patent Number:
11264458
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a…
Machine-learning driven prediction in integrated circuit design
Granted: February 22, 2022
Patent Number:
11256845
Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.
Efficient calculation of ED25519/448 signature verification in an encryption device
Granted: February 15, 2022
Patent Number:
11251973
A computer system module(s) substitutes a double scalar multiplication, used for signature verification in an encryption/decryption system, for two single scalar multiplications. The modules verify a group equation defined by [S]B=R+[k]A? of the encryption/decryption system, where S is an integer characterized by the signature, K is an integer generated by a message being encrypted, B is a base point on the elliptic curve, R is a point on the elliptic curve and characterized by the…
Adaptive parallelization for multi-scale simulation
Granted: February 15, 2022
Patent Number:
11249813
Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result…
Verifying glitches in reset path using formal verification and simulation
Granted: February 1, 2022
Patent Number:
11238202
A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the…
Layout-aware test pattern generation and fault detection
Granted: February 1, 2022
Patent Number:
11237210
Methods and apparatuses to assign faults to nets in an integrated circuit (IC) are described. Each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins. During operation, a fan-out structure of a net can be partitioned into a set of non-overlapping subnets and a set of branch nodes, wherein each branch node electrically couples three or more non-overlapping subnets. Next, each branch node can be represented…
Augmenting an integrated circuit (IC) design simulation model to improve performance during verification
Granted: January 25, 2022
Patent Number:
11231462
An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can…
Single flux quantum circuit that includes a sequencing circuit
Granted: January 25, 2022
Patent Number:
11233516
A single flux quantum (SFQ) circuit can include a combinational logic network, which can include a set of SFQ logic cells. The SFQ circuit can also include an SFQ sequencing circuit, which can be used to generate delayed versions of clock pulses to clock the set of SFQ logic cells.
SAT solver based on interpretation and truth table analysis
Granted: January 25, 2022
Patent Number:
11232174
Techniques and systems for solving Boolean satisfiability (SAT) problems are described. Some embodiments solve SAT problems using efficient construction of truth tables. Some embodiments can improve performance of SAT solvers by using truth tables instead of incurring the overhead of Conjunctive Normal Form (CNF) conversion.
System for serializing high speed data signals
Granted: January 11, 2022
Patent Number:
11223469
A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that…
Mask rule checking for curvilinear masks for electronic circuits
Granted: January 11, 2022
Patent Number:
11222160
A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two…
Method and apparatus for reducing pessimism of graph based static timing analysis
Granted: January 11, 2022
Patent Number:
11222155
Disclosed is a method and apparatus that takes timing information associated with a plurality of inputs to a cell, such as an AND-gate, within an integrated circuit (IC) design, store the timing information in a timing information register (TIR) associated with an index identifying the source of the timing information and track the source of the timing information for a predetermined number of cells through the index. The timing information in the TIRs is merged upon the index indicating…
State table complexity reduction in a hierarchical verification flow
Granted: January 11, 2022
Patent Number:
11222154
State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical…
Combinatorial and sequential logic compaction in electronic circuit design emulation
Granted: January 11, 2022
Patent Number:
11221864
An emulation host system can configure a reprogrammable hardware emulation system to emulate an electronic circuit design. The emulation host system can analyze the electronic circuit design for electronic circuits that are repetitive. The emulation host system can partition the electronic circuits onto a single partition. The emulation host system can map the single partition onto a single programmable logic element (PLE) of the reprogrammable hardware emulation system. The emulation…
Mitigating timing yield loss due to high-sigma rare-event process variation
Granted: December 28, 2021
Patent Number:
11210448
Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is…
3D resist profile aware resolution enhancement techniques
Granted: December 14, 2021
Patent Number:
11200362
Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.
Waveform based reconstruction for emulation
Granted: December 14, 2021
Patent Number:
11200149
A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
Automated self-check of a closed loop emulation replay
Granted: December 14, 2021
Patent Number:
11200127
A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting…
FPGA-based hardware emulator system with an inter-FPGA connection switch
Granted: December 7, 2021
Patent Number:
11194943
A hardware emulation system for emulating an integrated circuit design under test (DUT) includes a switch system, FPGAs and serial transmitter and receiver circuitry. The switch system has input and output ports and is configurable to change which ports are connected to each other. The FPGAs are configurable to emulate a functionality of the DUT. The functionality of the DUT is partitioned across multiple FPGAs. The serial transmitter circuitry transmits data from the FPGAs on serial…
