Identifying software components in a software codebase
Granted: April 21, 2020
Patent Number:
10628577
Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching software files. In an embodiment, the reference database may store a…
Providing guidance to an equivalence checker when a design contains retimed registers
Granted: April 21, 2020
Patent Number:
10628545
Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker,…
Modulization of cache structure utilizing independent tag array and data array in microprocessor
Granted: April 21, 2020
Patent Number:
10628320
Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues that comprise, upon occurrence of a conflict between at least one instruction requesting…
Gate oxide breakdown in OTP memory cells for physical unclonable function (PUF) security
Granted: April 14, 2020
Patent Number:
10623192
Gate oxide breakdown in the programming element of an OTP (One-Time Programmable) memory cell can vary widely. The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array is described.
Automatically generated schematics and visualization
Granted: April 14, 2020
Patent Number:
10621298
An automated visualization tool in a command line environment allows complex log data to be represented by symbols and associated information for clarity of communication and better understanding of the associated design.
Generating SAIF efficiently from hardware platforms
Granted: April 14, 2020
Patent Number:
10621296
A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the…
Semi-local ballistic mobility model
Granted: April 14, 2020
Patent Number:
10621294
A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the…
Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions
Granted: April 7, 2020
Patent Number:
10613859
An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a…
Graphical view and debug for coverage-point negative hint
Granted: March 31, 2020
Patent Number:
10606977
The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in…
Fast locking clock and data recovery circuit
Granted: March 31, 2020
Patent Number:
10608645
A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock…
Atomic scale grid for modeling semiconductor structures and fabrication processes
Granted: March 31, 2020
Patent Number:
10606968
Roughly described, a system for simulating a temporal process in a body includes a meshing module to impose a grid of nodes on the body, the grid having a uniform node spacing which is less than the quantum separation distance in silicon. A system of node equations is provided, including at least one node equation for each of a plurality of nodes of the grid. The node equations describe behavior of at least one physical quantity at that node through each time step of the process. An…
Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits
Granted: March 31, 2020
Patent Number:
10605863
Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the…
Using a layer performance metric (LPM) to perform placement, routing, and/or optimization of an integrated circuit (IC) design
Granted: March 24, 2020
Patent Number:
10599882
Techniques and systems for using a layer performance metric (LPM) during integrated circuit (IC) design are described. Some embodiments can compute an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path. Next, the embodiments can use the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.
Formal clock network analysis, visualization, verification and generation
Granted: March 24, 2020
Patent Number:
10599800
Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration…
Efficient power analysis
Granted: March 24, 2020
Patent Number:
10599794
Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected…
Topography simulation of etching and/or deposition on a physical structure
Granted: March 24, 2020
Patent Number:
10599789
Systems and techniques are described for topography simulation of etching and/or deposition on a physical structure. The structural information can be represented using a three-dimensional (3D) voxel grid data structure. For each particle emitted by a Monte-Carlo particle emission model, a topographical modification caused by the particle can be determined by (1) calculating fluxes, (2) evaluating surface reactions, and (3) modifying the physical structure. The effect of the etching…
Reversing the effects of hot carrier injection and bias threshold instability in SRAMs
Granted: March 10, 2020
Patent Number:
10586588
The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for detrapping charges in gate dielectrics in P-channel pull-up transistors and N-channel pull-down transistors in a portion of a static random access memory (SRAM) array due to hot carrier injection (HCI), negative bias temperature instability (NBTI) and positive bias instability (PBTI). This Abstract is not intended to limit the scope of the claims.
Automated root-cause analysis, visualization, and debugging of static verification results
Granted: March 10, 2020
Patent Number:
10586001
Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug…
Generation of workload models from execution traces
Granted: March 3, 2020
Patent Number:
10579341
Methods and computer readable media for software modeling. The method comprises accessing one or more software execution traces describing execution times of tasks within software executed on a target platform. The method also comprises generating a workload model of the software based on the one or more software execution traces of the software executed on the target platform. The workload model describes tasks of the software and workloads on the target platform associated with the…
Force/release support in emulation and formal verification
Granted: March 3, 2020
Patent Number:
10579760
Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the…
