Multi-scale simulation including first principles band structure extraction
Granted: June 16, 2020
Patent Number:
10685156
Electronic design automation modules include a first tool and a second tool. The first tool includes ab initio simulation procedures configured to use input parameters to produce information about a band structure of a simulated material on a first simulation scale specified at least in part by the input parameters. The second tool includes a simulation procedure configured to used information about the band structure of the simulated material produced by the first tool to extract…
Enhancing memory yield and performance through utilizing nanowire self-heating
Granted: June 9, 2020
Patent Number:
10679719
A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a…
Performance aware word line under-drive read assist scheme for high density SRAM to enable low voltage functionality
Granted: June 9, 2020
Patent Number:
10679694
PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and…
Exponentially fitted approximation for anisotropic semiconductor equations
Granted: June 9, 2020
Patent Number:
10678972
Roughly described, a method for determining characteristics of a body by simulation, useful in analyzing semiconductor devices, includes imposing a Delaunay mesh on a simulated body to be modeled, determining a system of node equations describing generation and flux of a set of at least a first physical quantity at each node in the mesh, and numerically solving the system of node equations to identify the physical quantities in the set at each node in the mesh, where the flux of the…
Protection scheme for embedded code
Granted: June 9, 2020
Patent Number:
10678710
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a…
Method and apparatus of using parity to detect random faults in memory mapped configuration registers
Granted: June 9, 2020
Patent Number:
10678634
A fault detection circuit generates a current parity bit for configuration data currently stored in a configuration register during each clock cycle, and compares the current parity bit with a previous parity bit generated during a previous clock cycle. An error signal is asserted when a mismatch is detected, indicating that the configuration register data erroneously changed due to a random hardware fault. Detection output circuitry is used to disable the error signal output driver…
Logic timing and reliability repair for nanowire circuits
Granted: May 26, 2020
Patent Number:
10665320
A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. A repair circuit can be…
Lithographic mask functions to model the incident angles of a partially coherent illumination
Granted: May 19, 2020
Patent Number:
10656528
In the embodiments disclosed herein, an approach based on a mask function M is disclosed. This approach meets the requirement of the Hopkins model and at the same time incorporates the incident angle effects of a given partially coherent illumination. The new mask function M is referred to as a partially coherent mask function (PCMF). In the embodiments disclosed herein, the incident angle effects of individual source points of a given partially coherent illumination are removed from the…
Multi-level clock and data recovery circuit
Granted: May 19, 2020
Patent Number:
10659214
A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second,…
Using runtime information from solvers to measure quality of formal verification
Granted: May 19, 2020
Patent Number:
10657307
Systems and techniques are described for using runtime information to identify a verification hole and/or compute a verification metric. Runtime information (RI) for a set of proven assertions can be determined, wherein the RI includes a first set of registers, a first set of inputs, and a first set of constraints that were used by a formal verification engine during runtime to prove one or more assertions for a design under verification (DUV). Next, a second set of registers, a second…
Memory bypass function for a memory
Granted: May 12, 2020
Patent Number:
10650906
A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit…
Video overlay
Granted: May 12, 2020
Patent Number:
10650509
A method includes automatically aligning a laser-based timing analysis image of a semiconductor device with an image of a layout of the device. The method further includes controlling a speed at which a multitude of images subsequently obtained by the laser-based timing analysis are compared to the layout of the device to create a video overlay. The method further includes analyzing a multitude of potential failures of the semiconductor device by detecting movements of a multitude of…
Method for testing computer program product
Granted: May 12, 2020
Patent Number:
10650145
This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one signature set of binary data from a read-only section of the reference computer program library, wherein the at least one signature set of binary data is determined to…
Boolean satisfiability (SAT) solver
Granted: May 12, 2020
Patent Number:
10650109
Techniques and systems for solving a Boolean satisfiability (SAT) problem are described. Specifically, embodiments solve the SAT problem by generating an extended resolution proof. It is well-known that many technological problems can be modeled as SAT problems, and that solving an underlying SAT problem effectively solves the original technological problem. Therefore, embodiments described herein can be used to solve any technological problem that can be modeled as a SAT problem.
Normally-off gallium oxide field-effect transistor
Granted: May 5, 2020
Patent Number:
10644107
The independent claims of this patent signify a concise description of embodiments. Disclosed herein is a normally-off, gallium oxide field-effect transistor. The field-effect transistor comprises a source, a source spacer, a first channel region, a second channel region, a drain spacer, and a drain. The source, the source spacer, the first channel region, the second channel region, the drain spacer, and the drain are of a first conductivity type. All the regions have the same type of…
Concurrent formal verification of logic synthesis
Granted: May 5, 2020
Patent Number:
10643012
Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.
Simulation modeling frameworks for controller designs
Granted: April 28, 2020
Patent Number:
10635843
A method for enabling user-customization of a controller design for simulation comprises accessing at least one library of individual simulation component models for controller components. The method further comprises receiving information describing an architecture of a customized controller design corresponding to a controller that controls communications between other parts of a first target system. The method additionally comprises generating a controller simulation model for the…
Producing mask layouts with rounded corners
Granted: April 28, 2020
Patent Number:
10635776
A two-dimensional representation of a polygon is converted to a parametric representation. A smoothing filter is applied to the parametric representation to produce corner rounding. In some embodiments, a polygon layout plus a model that specifies how much corner rounding should be applied are taken as inputs. The desired amount of rounding to the corners in the input polygons is applied and this produces a new polygon layout with corners that are properly rounded as its output. The…
Layer class relative density for technology modeling in IC technology
Granted: April 28, 2020
Patent Number:
10634992
A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.
Providing guidance to an equivalence checker when a design contains retimed registers
Granted: April 21, 2020
Patent Number:
10628545
Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker,…
