Verification of Ethernet hardware based on checksum correction with cyclic redundancy check
Granted: May 7, 2024
Patent Number:
11979232
A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC)…
Enforcing mask synthesis consistency across random areas of integrated circuit chips
Granted: May 7, 2024
Patent Number:
11977327
A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties…
Modifying segments and vertices of mask shapes for mask synthesis
Granted: May 7, 2024
Patent Number:
11977324
In some aspects, a mask shape is represented by vertices that are connected by segments. A correction to the mask shape is received. The correction may include displacements of the segments and displacements of the vertices. The mask shape is modified by a processor, as follows. The segments are moved according to the segment displacements. As part of this process, vertices that are endpoints of the moved segments are replicated. The replicated vertices are then collapsed. The resulting…
Phase mixer non-linearity measurement within clock and data recovery circuitry
Granted: April 30, 2024
Patent Number:
11973508
A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined…
Parameterized superconducting multi-row circuit
Granted: April 30, 2024
Patent Number:
11973497
A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.
Automatic elastic CPU for physical verification
Granted: April 30, 2024
Patent Number:
11972193
Disclosed herein are a method, a system, and a computer-readable storage-medium embodiments of automatic elastic CPU for a physical verification job. An embodiment includes generating multiple commands for a physical verification job of a design. The multiple commands are related by a dependency graph. The embodiment further includes allocating an initial amount of computing resources to execute the multiple commands, queuing a subset of the multiple commands for execution based on the…
Superseding design rule check (DRC) rules in a DRC-correct interactive router
Granted: April 30, 2024
Patent Number:
11972192
Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a…
System and method for providing enhanced net pruning
Granted: April 30, 2024
Patent Number:
11972191
A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the…
Emulation performance analysis using abstract timing graph representation
Granted: April 23, 2024
Patent Number:
11966677
A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of…
Modelling timing behavior using augmented sensitivity data for physical parameters
Granted: April 23, 2024
Patent Number:
11966678
A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known…
Phase mixer non-linearity compensation within clock and data recovery circuitry
Granted: April 16, 2024
Patent Number:
11962676
A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines…
Partitioning in post-layout circuit simulation
Granted: April 16, 2024
Patent Number:
11960811
New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the…
Classification of programming language code into basic constructs of source code and non-source code
Granted: April 9, 2024
Patent Number:
11954485
A method for processing a source code file comprises scanning the source code file to identify text lines, and analyzing, via one or more processors, the text lines with a classifier to identify one or more of the text lines that correspond to code construct type information. The code construct type information includes license information. The classifier is trained with sample source code files. The method further comprises generating a subset of the text lines that excludes the one or…
Two-step duty-cycle correction for high-speed clocks in communications systems
Granted: April 2, 2024
Patent Number:
11949421
A method and system for performing duty-cycle correction (DCC) on a clock signal is provided. The method provides a two-step duty cycle correction. The method can include performing a main DCC of a single-ended clock signal, to generate a duty cycle adjusted single-ended clock signal, wherein a duty cycle of the single-ended clock signal is corrected according to a received duty-cycle continuous control signal and converting the duty cycle adjusted single-ended clock signal to…
Intelligent software development, security, and operations workflow
Granted: April 2, 2024
Patent Number:
11947946
Disclosed herein are system, computer-implemented method, and computer program product (computer-readable storage medium) embodiments for implementing an intelligent DevSecOps workflow. An embodiment includes receiving, by at least one processor, a risk profile associated with a software deployment, and an update related to the software deployment; and evaluating, by the at least one processor, at least one parameter associated with the update, to produce an evaluation result.…
Low-power static signoff verification from within an implementation tool
Granted: April 2, 2024
Patent Number:
11947885
In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination…
Universal serial bus scheduling using real time data
Granted: April 2, 2024
Patent Number:
11947480
A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes…
Automated equal-resistance routing in compact pattern
Granted: March 26, 2024
Patent Number:
11941339
Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is…
Energy-efficient SFQ logic biasing technique
Granted: March 26, 2024
Patent Number:
11942936
Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being…
Accelerating static program analysis with artifact reuse
Granted: March 26, 2024
Patent Number:
11941379
A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked…
