Accurate calibration of analog integrated-circuits continuous-time complex filters
Granted: July 2, 2024
Patent Number:
12028034
A first and second input tone are applied to a continuous-time complex filter within an integrated circuit. The magnitude of the output of the filter at the frequency of each of the first and second input tones are measured and compared to determine the value of a filter tuning control signal. A tuning control signal is applied to the filter with the determined value to tune the filter.
Memory optimization for storing objects in nested hash maps used in electronic design automation systems
Granted: July 2, 2024
Patent Number:
12026202
Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which…
Varied validity bit placement in tag bits of a memory
Granted: July 2, 2024
Patent Number:
12026094
A system and method access memory blocks in a memory by receiving a memory transaction request from a processing device. First hash bits of the memory transaction request are compared with second hash bits of a first memory block of a memory. Data associated with the first memory block is output to the processing device based on the comparison of the first hash bits with the second hash bits.
Virtual isolated pattern layer: isolated pattern recognition, extraction and compression
Granted: June 25, 2024
Patent Number:
12019966
A method includes identifying isolated shapes within a semiconductor design. The isolated shapes correspond to patterns of layers of components of the semiconductor design. The method also includes identifying one or more unique patterns among the isolated shapes, generating a virtual isolated pattern layer including data associated with the isolated shapes and the one or more unique patterns, determining whether a unique pattern of the one or more unique patterns satisfies a design rule…
Mixed-precision neural networks
Granted: June 18, 2024
Patent Number:
12015526
Techniques for mixed precision quantization of a machine learning (ML) model. A target bandwidth increase is received (302), for the ML model (114) including objects of a first data type represented by a first number of bits. The target bandwidth increase relates to changing a first portion of the objects to a second data type represented by a second number of bits different from the first number of bits (310). The method further includes sorting the objects in the ML model based on…
Testable time-to-digital converter
Granted: June 18, 2024
Patent Number:
12015411
A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of…
Deconvolution by convolutions
Granted: June 18, 2024
Patent Number:
12014262
Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. An embodiment includes a convolution processor that includes hardware implementing logic to perform at least one algorithm comprising a convolution algorithm. The at least one convolution processor may be further configured to perform operations including performing a first convolution and outputting a first deconvolution segment as a result…
Advanced register merging
Granted: June 18, 2024
Patent Number:
12014205
Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for advanced register merging. A first register-merging operation may be configured to merge, into a first survivor register, a first plurality of registers of the RTL description. A second register-merging operation configured to merge, into a first equivalence class, a second plurality of registers that share a first functional equivalency…
Transforming a logical netlist into a hierarchical parasitic netlist
Granted: June 18, 2024
Patent Number:
12014127
A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on…
Instance instrumentation for different data sources
Granted: June 11, 2024
Patent Number:
12008373
Instance instrumentation is provided for different data sources by identifying an instance of a function in a program that receives input from an untrusted source; and replacing, at runtime of the program, the instance of the function with an instrumented version of the function that includes a marking function to indicate an output of the instrumented version of the function is tainted by the input received from the untrusted source. Additionally, instance instrumentation can be…
Cell overlap violation diagnostics with machine learning
Granted: June 11, 2024
Patent Number:
12008303
A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by…
High bandwidth integrated multiplexer and driver stage for transmitter
Granted: June 4, 2024
Patent Number:
12003233
A system for serializing data includes, in part, serialization circuitry configured to convert input data provided through parallel input streams into a lesser number of parallel output streams. The input data is converted through sampling based on a set of clock signals that are phase-offset. The system further includes a pre-driver circuit having combinational logic including a first multiplexer. The first multiplexer is configured to generate an output of the pre-driver circuit…
Embedded memory transparent in-system built-in self-test
Granted: June 4, 2024
Patent Number:
12002530
A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system…
Analog centric current modeling within a digital testbench in mixed-signal verification
Granted: June 4, 2024
Patent Number:
12001770
A method includes operating a digital simulator to mimic loading effects of digital circuit blocks of a circuit design on analog circuit blocks of the circuit design. The digital simulator sets a current signal timing and a current level value at an analog/digital boundary between the digital circuit aspects and the analog circuit aspects. The analog simulator is operated to apply the current signal timing and the current level value to simulate the analog circuit blocks.
Enhanced glitch estimation in vectorless power analysis
Granted: June 4, 2024
Patent Number:
12001768
A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.
Waveform based reconstruction for emulation
Granted: June 4, 2024
Patent Number:
12001317
A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
Smart regression test selection for software development
Granted: May 28, 2024
Patent Number:
11994979
A method of testing a change in a software code includes, searching a database of tests to identify a subset of the tests that include a function that executes the change, forming, from the subset, a multitude of groups each having a different execution path. The tests in the same group have the same execution path. The method further includes prioritizing the tests within each of the multitude of groups based on one or more testing characteristics, and selecting, from each of the…
Path margin monitor integration with integrated circuit
Granted: May 14, 2024
Patent Number:
11983032
The timing margin of various signal paths in an integrated circuit is monitored by components on the integrated circuit itself. Path margin monitor (PMM) circuits on the integrated circuit receive (a) functional signals propagating along signal paths in the integrated circuit, and (b) corresponding clock signals that are used to clock the functional signals. The PMM circuits output signals (PMM signals) which are indicative of the actual timing margins for the signal paths. For…
Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network
Granted: May 14, 2024
Patent Number:
11984384
Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the…
Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit
Granted: May 14, 2024
Patent Number:
11983474
A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified…
