Instance instrumentation for different data sources
Granted: June 11, 2024
Patent Number:
12008373
Instance instrumentation is provided for different data sources by identifying an instance of a function in a program that receives input from an untrusted source; and replacing, at runtime of the program, the instance of the function with an instrumented version of the function that includes a marking function to indicate an output of the instrumented version of the function is tainted by the input received from the untrusted source. Additionally, instance instrumentation can be…
Cell overlap violation diagnostics with machine learning
Granted: June 11, 2024
Patent Number:
12008303
A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by…
High bandwidth integrated multiplexer and driver stage for transmitter
Granted: June 4, 2024
Patent Number:
12003233
A system for serializing data includes, in part, serialization circuitry configured to convert input data provided through parallel input streams into a lesser number of parallel output streams. The input data is converted through sampling based on a set of clock signals that are phase-offset. The system further includes a pre-driver circuit having combinational logic including a first multiplexer. The first multiplexer is configured to generate an output of the pre-driver circuit…
Embedded memory transparent in-system built-in self-test
Granted: June 4, 2024
Patent Number:
12002530
A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system…
Analog centric current modeling within a digital testbench in mixed-signal verification
Granted: June 4, 2024
Patent Number:
12001770
A method includes operating a digital simulator to mimic loading effects of digital circuit blocks of a circuit design on analog circuit blocks of the circuit design. The digital simulator sets a current signal timing and a current level value at an analog/digital boundary between the digital circuit aspects and the analog circuit aspects. The analog simulator is operated to apply the current signal timing and the current level value to simulate the analog circuit blocks.
Enhanced glitch estimation in vectorless power analysis
Granted: June 4, 2024
Patent Number:
12001768
A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.
Waveform based reconstruction for emulation
Granted: June 4, 2024
Patent Number:
12001317
A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.
Smart regression test selection for software development
Granted: May 28, 2024
Patent Number:
11994979
A method of testing a change in a software code includes, searching a database of tests to identify a subset of the tests that include a function that executes the change, forming, from the subset, a multitude of groups each having a different execution path. The tests in the same group have the same execution path. The method further includes prioritizing the tests within each of the multitude of groups based on one or more testing characteristics, and selecting, from each of the…
Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit
Granted: May 14, 2024
Patent Number:
11983474
A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified…
Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network
Granted: May 14, 2024
Patent Number:
11984384
Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the…
Path margin monitor integration with integrated circuit
Granted: May 14, 2024
Patent Number:
11983032
The timing margin of various signal paths in an integrated circuit is monitored by components on the integrated circuit itself. Path margin monitor (PMM) circuits on the integrated circuit receive (a) functional signals propagating along signal paths in the integrated circuit, and (b) corresponding clock signals that are used to clock the functional signals. The PMM circuits output signals (PMM signals) which are indicative of the actual timing margins for the signal paths. For…
Verification of Ethernet hardware based on checksum correction with cyclic redundancy check
Granted: May 7, 2024
Patent Number:
11979232
A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC)…
Enforcing mask synthesis consistency across random areas of integrated circuit chips
Granted: May 7, 2024
Patent Number:
11977327
A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties…
Modifying segments and vertices of mask shapes for mask synthesis
Granted: May 7, 2024
Patent Number:
11977324
In some aspects, a mask shape is represented by vertices that are connected by segments. A correction to the mask shape is received. The correction may include displacements of the segments and displacements of the vertices. The mask shape is modified by a processor, as follows. The segments are moved according to the segment displacements. As part of this process, vertices that are endpoints of the moved segments are replicated. The replicated vertices are then collapsed. The resulting…
Phase mixer non-linearity measurement within clock and data recovery circuitry
Granted: April 30, 2024
Patent Number:
11973508
A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined…
Parameterized superconducting multi-row circuit
Granted: April 30, 2024
Patent Number:
11973497
A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.
Automatic elastic CPU for physical verification
Granted: April 30, 2024
Patent Number:
11972193
Disclosed herein are a method, a system, and a computer-readable storage-medium embodiments of automatic elastic CPU for a physical verification job. An embodiment includes generating multiple commands for a physical verification job of a design. The multiple commands are related by a dependency graph. The embodiment further includes allocating an initial amount of computing resources to execute the multiple commands, queuing a subset of the multiple commands for execution based on the…
Superseding design rule check (DRC) rules in a DRC-correct interactive router
Granted: April 30, 2024
Patent Number:
11972192
Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a…
System and method for providing enhanced net pruning
Granted: April 30, 2024
Patent Number:
11972191
A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the…
Emulation performance analysis using abstract timing graph representation
Granted: April 23, 2024
Patent Number:
11966677
A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of…
