D-type wholly dissimilar high-speed static set-reset flip flop
Granted: January 2, 2024
Patent Number:
11863187
A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a…
Unwanted peak reduction in equalizer
Granted: January 2, 2024
Patent Number:
11863170
An equalizer circuit includes: a main stage circuit including: a main stage differential pair; and a main stage degeneration resistance; a replica stage circuit including: a replica stage differential pair matching the main stage differential pair; and a replica stage degeneration resistance matching the main stage degeneration resistance and disconnected from the replica stage differential pair; equalizer inputs connected to: gate electrodes of the main stage differential pair; and gate…
Segregating defects based on computer-aided design (CAD) identifiers associated with the defects
Granted: January 2, 2024
Patent Number:
11861286
For each defect in a set of defects, the defect may be associated with a defect attribute constructed from a set of computer-aided design (CAD) identifiers associated with polygons in an integrated circuit (IC) design that overlap with a defect area of the defect. Next, the set of defects may be segregated into defect groups based on the associated defect attributes. The defect groups may be used to perform additional processing on the set of defects.
Deterministic data latency in serializer/deserializer-based design for test systems
Granted: January 2, 2024
Patent Number:
11860751
Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals.…
Skeleton representation of layouts for the development of lithographic masks
Granted: January 2, 2024
Patent Number:
11860531
In certain embodiments, a method includes the following steps. A layout used in a lithographic mask development process is accessed. For example, the layout may be the layout of the mask itself, or it may be the layout of the resulting printed pattern on the wafer. The layout includes a number of disjoint shapes. Skeleton representations for at least some of the disjoint shapes in the layout are determined. The skeleton representation of an individual shape has elements of two or more…
Machine learning delay estimation for emulation systems
Granted: January 2, 2024
Patent Number:
11860227
A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and…
Machine-learning enhanced compiler
Granted: December 26, 2023
Patent Number:
11853662
A method includes storing a base model generated using base data and receiving training data generated by compiling circuit designs. The method also includes generating, using the training data, a tuned model and generating, using the training data and the base data, a hybrid model. The method further includes receiving a selected cost function and biasing the base model, the tuned model, and the hybrid model using the selected cost function.
Incremental routing based pin assignment
Granted: December 26, 2023
Patent Number:
11853680
The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design…
FPGA implementation interleaved with FPGA overlay architectures for emulation
Granted: December 26, 2023
Patent Number:
11853668
A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected…
Performing hardware description language transformations
Granted: December 26, 2023
Patent Number:
11853665
Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be…
Enriched auto command feature for I3C host controller
Granted: December 26, 2023
Patent Number:
11853236
A device includes a memory, a plurality of registers, a multiplexer/demultiplexer circuit, and a controller circuit. The memory stores a plurality of pages of pointers and a table of commands. The plurality of registers store information about a plurality of target devices. The multiplexer/demultiplexer circuit selects (i) information from a register of the plurality of registers based on a request received from a target device of the plurality of target devices, (ii) a page from the…
Interference reducing passive transmission line receiver
Granted: December 19, 2023
Patent Number:
11848676
The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching…
Integrated circuit design using multi-bit combinational cells
Granted: December 19, 2023
Patent Number:
11847396
Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell…
Automated determinaton of failure mode distribution
Granted: December 12, 2023
Patent Number:
11842134
A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a…
Multi-cycle power analysis of integrated circuit designs
Granted: December 12, 2023
Patent Number:
11842132
A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with…
Automatic global clock tree synthesis
Granted: December 5, 2023
Patent Number:
11836000
A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second…
CFET architecture for balancing logic library and SRAM bitcell
Granted: December 5, 2023
Patent Number:
11837280
The independent claims of the present disclosure signify a concise description of embodiments. An electronic structure based on complementary-field effect transistor (CFET) architecture is disclosed. The electronic structure comprises an n-channel metal-oxide-semiconductior (NMOS) gate-all-around (GAA) channel in a first layer, and p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer. The PMOS GAA channel is wider compared to the NMOS GAA channel. The first layer is…
Machine learning-based prediction of metrics at early-stage circuit design
Granted: December 5, 2023
Patent Number:
11836641
When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML)…
Memory instance reconfiguration using super leaf cells
Granted: December 5, 2023
Patent Number:
11836433
A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected…
Engineering change orders with consideration of adversely affected constraints
Granted: December 5, 2023
Patent Number:
11836425
In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related…
