Freeform optical surface and method of forming a freeform optical surface
Granted: October 31, 2023
Patent Number:
11803051
A freeform optical surface includes, in part, an off-axis optical surface and a departure optical module. The off-axis optical surface may be an off-axis conic optical surface. The departure optical module may be substantially perpendicular to the off-axis conic optical surface.
Compiler-based code generation for post-silicon validation
Granted: October 24, 2023
Patent Number:
11796593
Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon…
Scalable supply multiplexer circuit
Granted: October 24, 2023
Patent Number:
11799480
A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning…
Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design
Granted: October 24, 2023
Patent Number:
11797742
A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value…
Endpoint path margin based integrated circuit design using sub-critical timing paths
Granted: October 24, 2023
Patent Number:
11797739
Techniques for integrated circuit (IC) design are disclosed. A path margin is determined for an endpoint of a plurality of timing paths for an IC design. This includes identifying a sub-critical path, among the plurality of timing paths, where the sub-critical path has more slack than a critical path relating to the endpoint. The path margin is generated based on a first slack associated with the sub-critical path. A second slack, relating to at least one of the plurality of timing…
Finding equivalent classes of hard defects in stacked MOSFET arrays
Granted: October 24, 2023
Patent Number:
11797737
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the…
Regression testing based on overall confidence estimating
Granted: October 24, 2023
Patent Number:
11797735
A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results,…
Single-pass diagnosis for multiple chain defects
Granted: October 17, 2023
Patent Number:
11789077
Disclosed herein are method, system, and storage-medium embodiments for single-pass diagnosis of multiple chain defects in circuit-design testing. Embodiments include processor(s) to select a plurality of a scan chains in a circuit under test and determine presence of at least a first defect in the first scan chain, and a second defect in the first scan chain or in the second scan chain. The plurality of scan chains may include specific scan chains that each have respective pluralities…
Full correlation aging analysis over combined process voltage temperature variation
Granted: October 17, 2023
Patent Number:
11790127
A method, a system, and non-transitory computer readable medium for aging analysis are provided. The method includes performing stress simulations for a plurality of process, voltage, temperature (PVT) conditions for a circuit, the circuit including one or more devices, extrapolating device level stresses obtained from the stress simulations into device level parameter degradations to a desired circuit age; and performing degradation simulations for the circuit for the same PVT…
Placement and simulation of cell in proximity to cell with diffusion break
Granted: October 17, 2023
Patent Number:
11790150
A system and method for placement and simulation of a cell in proximity to a cell with a diffusion break is herein disclosed. According to one embodiment, an integrated circuit is designed to include a first cell that has a first edge and a second edge opposite the first edge. The first cell may also include a diffusion region that extends from the first edge to the second edge with a diffusion break separating the diffusion region. The diffusion break may be spaced away from the second…
Waveform construction using interpolation of data points
Granted: October 10, 2023
Patent Number:
11784783
A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.
System and method for auditing a graph-based API
Granted: October 3, 2023
Patent Number:
11775363
A method for auditing a graph-based API includes obtaining a structure describing object types of the API and fields of the object types. A schema graph of the structure is generated including nodes representing object types. The nodes are connected by directed edges representing field resolution between object types. A line graph is generated and includes a node in place of each edge of the schema graph and edges in place of nodes of the schema graph. Frontiers of the line graph are…
High speed, low hardware footprint waveform
Granted: October 3, 2023
Patent Number:
11775716
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces…
Fin patterning to reduce fin collapse and transistor leakage
Granted: October 3, 2023
Patent Number:
11776816
At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.
Inverse lithography and machine learning for mask synthesis
Granted: September 19, 2023
Patent Number:
11762283
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108).…
Coherent observability and controllability of overlaid clock and data propagation in emulation and prototyping
Granted: September 19, 2023
Patent Number:
11763053
The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed.…
Method and system for custom model definition of analog defects in an integrated circuit
Granted: September 19, 2023
Patent Number:
11763056
A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied,…
Net-based wafer inspection
Granted: September 19, 2023
Patent Number:
11763059
A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are…
Aging-resistant Schmitt receiver circuit
Granted: September 19, 2023
Patent Number:
11764765
A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.
Latency offset in pre-clock tree synthesis modeling
Granted: June 20, 2023
Patent Number:
11681842
Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint…
