Honoring pin insertion delay during clock tree synthesis
Granted: April 7, 2020
Patent Number:
10614261
Aspects of the present disclosure address systems and methods for dynamically adjusting skew windows during clock tree synthesis (CTS). A method may include identifying a pin insertion delay (PID) assigned to a clock sink in a set of clock sinks of a buffer tree in an integrated circuit design. The method further includes determining a skew window for the clock sink based on a skew target and adjusting the skew window based on identifying the PID assigned to the clock sink. The skew…
Constrained metric optimization of a system on chip
Granted: March 31, 2020
Patent Number:
10607039
A method including receiving a first configuration of a device validated against a design constraint, is provided. A configuration includes stimuli controls and stimuli parameters used as inputs in a device model. The method includes determining a quality of the first configuration based on an estimation of an output parameter including a desired behavior of the device, simulating the device in the first configuration when the first configuration quality overcomes a threshold, and…
System and method for dynamic visual guidance of mutually paired components in a circuit design editor
Granted: March 31, 2020
Patent Number:
10606974
In an electronic circuit design system, dynamic visual guidance for relative placement of mutually paired electronic components, such as a bypass capacitance portion and a power pin in a power domain, is provided. A first, selected component is adaptively paired with one of a plurality of second components eligible for pairing with the first component, according to predetermined pairing criteria such as proximity criteria. A mutual placement zone between the paired components is…
System, method, and computer program product for grouping one or more failures in a formal verification
Granted: March 24, 2020
Patent Number:
10599797
The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing linting analysis using structural and formal methods of at least a portion of the electronic design. Embodiments may also include identifying a plurality of failures from the formal verification and identifying one or more of the plurality of failures as having a similar root cause.…
Data aggregation process
Granted: March 24, 2020
Patent Number:
10599642
The present disclosure relates to a system and method for linking GUI plug-ins with multiple data providers. Embodiments may include allowing, via one or more computing devices, at least one data provider access to a data abstraction layer. Embodiments may further include allowing at least one GUI plug-in access to the data abstraction layer and receiving, at the data abstraction layer, a query from the at least one GUI plug-in. In response to the query, embodiments may include…
Failing read count diagnostics for memory built-in self-test
Granted: March 17, 2020
Patent Number:
10593419
Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.
Method and system for processing verification tests for testing a design under test
Granted: March 17, 2020
Patent Number:
10592703
A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start…
Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design
Granted: March 17, 2020
Patent Number:
10591526
Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance…
System and method for pin automation for topology editing
Granted: March 10, 2020
Patent Number:
10586011
Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also…
Method and system for verification using combined verification data
Granted: March 10, 2020
Patent Number:
10586014
A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a…
System and method for generating non-design manipulation elements in an electronic design
Granted: March 10, 2020
Patent Number:
10586002
The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing an electronic design having a plurality of geometric elements and generating a non-design element. Embodiments may further include associating the non-design element with one of the plurality of geometric elements and storing the non-design element with the one of the plurality of geometric elements. Embodiments may also include displaying, at a…
Current modeling process
Granted: March 10, 2020
Patent Number:
10586000
The present disclosure relates to modeling the transient current of a partially simulated hierarchical gate-level electronic design. Embodiments may include providing a partially simulated hierarchical gate-level electronic design, wherein the design includes a design hierarchy having one or more leaf blocks associated therewith. Embodiments may also include identifying activity of sequential elements of the leaf blocks using simulation vectors, wherein the activity is used to estimate…
Systems and methods for routing a clock net with multiple layer ranges
Granted: March 3, 2020
Patent Number:
10579767
Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer…
Method and system for reconstructing a graph presentation of a previously executed verification test
Granted: March 3, 2020
Patent Number:
10579761
A method for reconstructing a graph representation of a previously executed verification test, may include obtaining a truncated chronicle of start time and end time messages of actions of the verification test that were logged during execution of the verification test on a design under test (DUT); using a processor, parsing and analyzing the start time and the end time messages to determine an order of the actions; using a processor, determining an order of other actions of said…
Address failure detection for memory devices having inline storage configurations
Granted: March 3, 2020
Patent Number:
10579470
Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of…
Protocol compliant high-speed DDR transmitter
Granted: February 18, 2020
Patent Number:
10566046
Implementations described herein relate to circuits and techniques increasing transmitter output speed. In some implementations, a circuit is described using a pull-up data path comprising a first flying capacitor, a first buffer, a thin-oxide PMOS device, and a thick-oxide PMOS device, a pull-down data path comprising a second flying capacitor, a second buffer, a thin-oxide NMOS device, and a thick-oxide NMOS device, wherein the pull-up data path and the pull-down data path are…
Electronic circuit design editor with overlay of layout and schematic design features
Granted: February 18, 2020
Patent Number:
10565342
A system and method for an interactive circuit layout design that provides spatially adaptive overlay indicative of parametric properties. A physical layout of an electrical circuit product is rendered on a display. At least one net of the physical layout is delineated into a plurality of net segments each having at least one physical property parametrically specified in a value therefor. For each net segment, a corresponding segment indicator is selectively rendered on the display,…
Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design
Granted: February 11, 2020
Patent Number:
10558780
Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design…
Electronic library and design generation using image and text processing
Granted: February 11, 2020
Patent Number:
10558774
The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for generating electronic design element symbols for electronic circuit design tool libraries and designs in any desired format. In embodiments, such electronic design element symbols can be generated from a datasheet or any other image using image processing, graphical shape and text recognition techniques. Embodiments use step by step processing to extract…
2D compression-based low power ATPG
Granted: February 4, 2020
Patent Number:
10551435
Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during…
