2D compression-based low power ATPG
Granted: February 4, 2020
Patent Number:
10551435
Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during…
EM-compliance topology in a tree router
Granted: February 4, 2020
Patent Number:
10551431
Described is an improved approach to implement EM analysis, where the analysis can be performed early stages of the design process. Tree-routing is implemented using a structural routing solution, where an automatic routing mechanism is performed to generate a complete routing tree. That routing tree is then used to perform topology-driven EM analysis at various stages of the design process.
Method and system for efficient re-determination of a data valid window
Granted: January 28, 2020
Patent Number:
10545866
Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.
System and method for measurement and adaptation of pulse response cursors to non zero values
Granted: January 28, 2020
Patent Number:
10547475
A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an…
Duty cycle correction system and method
Granted: January 28, 2020
Patent Number:
10547298
The present disclosure relates to an apparatus and method for correcting a duty cycle of at least one signal. The apparatus may comprise at least one set of inverters configured to receive the at least one signal and correct the duty cycle of the at least one signal at a correction location of a plurality of correction locations based upon, at least in part, a transmission rate mode of a plurality of transmission rate modes.
System, method, and computer program product for ranking and displaying violations in an electronic design
Granted: January 28, 2020
Patent Number:
10546084
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and performing formal verification upon at least a portion of the electronic design. Embodiments may further include identifying one or more violations associated with the formal verification and ranking the one or more violations, based upon, at least in part, one or more user-selectable variables. Embodiments may also…
System, method, and computer program product for improving coverage accuracy in formal verification
Granted: January 28, 2020
Patent Number:
10546083
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further…
Method and system for identifying potential causes of failure in simulation runs using machine learning
Granted: January 28, 2020
Patent Number:
10546080
A method for identifying a potential cause of a failure in simulation runs on a design under test (DUT) using machine learning is disclosed.
Auto-zeroing receiver for memory interface devices
Granted: January 28, 2020
Patent Number:
10545895
Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback…
High-speed low VT drift receiver
Granted: January 28, 2020
Patent Number:
10545889
Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from…
On demand data stream controller for programming and executing operations in an integrated circuit
Granted: January 21, 2020
Patent Number:
10541043
Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be…
Generating a power grid for an integrated circuit
Granted: January 21, 2020
Patent Number:
10540470
The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and…
System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design
Granted: January 21, 2020
Patent Number:
10540467
The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display…
Systems and methods for streaming waveform data during emulation run
Granted: January 21, 2020
Patent Number:
10540466
An exemplary emulation computer may allocate a portion of its emulation memory for capturing probe data during a runtime of emulating a device under test (DUT). The emulation computer may instantiate a plurality of streaming probes from dynamic netlists provided by a user. The streaming probes may capture non-transitory internal signals within the DUT and transmit the captured non-transitory internal signals to the allocated portion of the emulation memory, which in turn may store the…
Critical path aware voltage drop analysis of an integrated circuit
Granted: January 21, 2020
Patent Number:
10540464
The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the…
Method and system for functional safety verification
Granted: January 21, 2020
Patent Number:
10540461
A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data,…
Programmable, area-optimized bank group rotation system for memory devices
Granted: January 14, 2020
Patent Number:
10534565
A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and…
Method and system to transfer data between components of an emulation system
Granted: January 14, 2020
Patent Number:
10536553
An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the…
Power domain placement of circuit components in advance node custom design
Granted: January 14, 2020
Patent Number:
10534887
A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a…
Carry chain logic in processor based emulation system
Granted: January 14, 2020
Patent Number:
10534625
Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are…
