Carry chain logic in processor based emulation system
Granted: January 14, 2020
Patent Number:
10534625
Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are…
Programmable, area-optimized bank group rotation system for memory devices
Granted: January 14, 2020
Patent Number:
10534565
A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and…
Method and system for automated selection of a subset of plurality of validation tests
Granted: January 7, 2020
Patent Number:
10528691
A method for automated selection of a subset of a plurality of validation tests for testing a device under test (DUT), may include obtaining the plurality of validation tests; using a processor, obtaining from a user, via an input device, one or a plurality of conditions relating to one or a plurality of execution parameters; and using a processor, analyzing each of the validation tests to identify a subset of the validation tests that includes verification tests conforming to said one…
Verification process for IJTAG based test pattern migration
Granted: January 7, 2020
Patent Number:
10528689
A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least…
System and method for schematic-driven generation of input/output models
Granted: January 7, 2020
Patent Number:
10528688
Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected…
Estimation and visualization of a full probability distribution for circuit performance obtained with Monte Carlo simulations over scaled sigma sampling
Granted: January 7, 2020
Patent Number:
10528644
A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations…
Systems and methods for estimating the future electrical resistance of a wire of a partially routed net
Granted: December 31, 2019
Patent Number:
10521543
Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves…
System, method, and computer program product for range-based clock analysis associated with the formal verification of an electronic circuit design
Granted: December 31, 2019
Patent Number:
10521531
The present disclosure relates to a method for formal verification of an electronic design. Embodiments may include receiving, using a processor, an electronic design having a plurality of clock configurations associated therewith and identifying a target clock configuration associated with the electronic design. Embodiments may also include receiving a range of clock factor values from a user, wherein each clock factor value corresponds to a frequency of the target clock configuration.…
User interface to implement topology integrity throughout routing implementations
Granted: December 31, 2019
Patent Number:
10521097
Described herein is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where a routing system is implemented to generate a complete routing tree. A user interface is provided that captures users' design intent about topology of an electrical design, and the routing system adheres to that user's design intent about the topology throughout a layout process for the electrical design.
Method, system, and computer program product to implement snapping for an electronic design
Granted: December 24, 2019
Patent Number:
10515180
Disclosed is an approach to implement snapping techniques that aid the interactive, assisted, or automatic placement of layout instances or groups of layout instances for generating a legal placement layout while reducing or entirely eliminating any subsequent or separate performance of design rule checking with respect to the relevant design rules, constraints, or requirements governing the legality of the instances or groups of instances placed in the placement layout.
Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic design
Granted: December 24, 2019
Patent Number:
10515177
Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the…
System and method for visualizing component data routes
Granted: December 24, 2019
Patent Number:
10515176
The present disclosure relates to a computer-implemented method for visualizing one or more IP-XACT component data routes is provided. The method may include receiving, using at least one processor, an IP-XACT description of one or design elements including at least one target ingress interface, and at least one of an initiator egress interface, a memory map and an address space. The method may further include analyzing, using the at least one processor, the IP-XACT description of the…
Interface modeling for power analysis of an integrated circuit
Granted: December 24, 2019
Patent Number:
10515174
The present embodiments relate to generation of an interface model for performing a power analysis on a hierarchical integrated circuit design. According to some aspects, embodiments relate to a method of power analysis. The method can include partitioning an integrated circuit design into at least a first partition and a second partition sharing an interface with the first partition. The method can include generating a connectivity database of a signal net traversing from the first…
System, method, and computer program product for computing formal coverage data compatible with dynamic verification
Granted: December 24, 2019
Patent Number:
10515169
The present disclosure is directed towards electronic circuit design and verification. Embodiments may include receiving, using a processor, source code corresponding to at least a portion of an electronic design and generating at least one coverage model for each of a dynamic verification and a formal verification. The method may further include determining a formal data set including stimuli coverage status, cone of influence coverage status, and proof coverage status and consolidating…
Systems and methods for routing track assignment
Granted: December 17, 2019
Patent Number:
10509878
Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first…
Systems and methods for reducing latency when transferring I/O between an emulator and target device
Granted: December 17, 2019
Patent Number:
10509877
Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another…
Instrumenting low power coverage counters in emulation
Granted: December 10, 2019
Patent Number:
10503243
Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes a method of hardware emulation on a computer. The method may include reading in, by the computer, a hardware description language file and a low power intent file and compiling the hardware description language file and the low power intent file into an emulation image. Embodiments may include loading, the emulation image into an emulator, running, the emulation image…
Electronic circuit design editor with off-screen violation display and correction
Granted: December 10, 2019
Patent Number:
10503862
A circuit editor generates a graphic rendering of an electronic circuit design for partial display in a visual canvas on a display unit. The circuit editor detects aberrant arrangements of circuit elements which violate predetermined circuit layout criteria, such as minimum spacing between the edges or corners of circuit elements, and forms a correction scheme to rearrange the circuit elements such that consistency with the circuit layout criteria is restored. When the aberrant…
Method, system, and computer program product for implementing group legal placement on rows and grids for an electronic design
Granted: December 10, 2019
Patent Number:
10503858
Disclosed are techniques for implementing group legal placement on rows and grids for an electronic design. These techniques identify a group comprising a plurality of instances. A proxy is identified from the plurality of instances. The group is placed in a row region based in part or in whole upon a plurality of permissible characteristics for the proxy without considering permissible characteristics of one or more remaining instances in the group. A group legality may be performed to…
Method and system for generating validation tests
Granted: December 10, 2019
Patent Number:
10503854
A method for generating a validation test, may include obtaining, using a processor, a validated scenario for generating a test for a verification model, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph. The method may also include analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with a faulty scheduler of a…
