Instrumenting low power coverage counters in emulation
Granted: December 10, 2019
Patent Number:
10503243
Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes a method of hardware emulation on a computer. The method may include reading in, by the computer, a hardware description language file and a low power intent file and compiling the hardware description language file and the low power intent file into an emulation image. Embodiments may include loading, the emulation image into an emulator, running, the emulation image…
Multiple injection lock ring-based phase interpolator
Granted: December 3, 2019
Patent Number:
10498345
Various embodiments described herein provide a multiple injection lock ring-based PI that can inject a plurality of clock signals, of different phases, at injection points disposed along the ring chain of the PI and lock phase to those received clock signals (injected clock signals). For instance, an embodiment described herein may provide a multiple injection lock ring-based PI that permits double injection, triple injection, or the like, of clock signals external into the PI.
Systems and methods for dynamically generating hierarchical rotating pcells from a static integrated circuit design
Granted: December 3, 2019
Patent Number:
10496772
Disclosed herein are embodiments for generating hierarchical rotating pcells (parametrized cells) design from a user provided static hierarchical design. An EDA (Electronic Design Automation) tool may receive a hierarchical static design and allow the user to instantiate a top level hierarchical rotating pcell using one or more parameters including an angle parameter to indicate a rotation angle. Based on the one or more parameters, the EDA tool may recursively identify, in the user's…
System and method for enhanced characterization for system identification of non-linear systems
Granted: December 3, 2019
Patent Number:
10496767
The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse…
Tree-routing for specific areas of an electronic design
Granted: November 26, 2019
Patent Number:
10489549
Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree, and specific portions of the design are routed individually from other portions of the design.
Support for multiple user defined assertion checkers in a multi-FPGA prototyping system
Granted: November 26, 2019
Patent Number:
10489534
A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a…
System and method for electronic circuit design editing having adaptive visual indicia for relative current loading of circuit layout portions
Granted: November 19, 2019
Patent Number:
10482211
In an electronic circuit design system, a physical layout of at least part of an electronic circuit design is visually rendered. Magnitude of current loading are determined at one or more of the circuit nodes, or one or more clusters of nodes grouped according to predetermined clustering criteria, for a selected net or nets. The range of magnitudes is mapped to at least one gradation range for visual indicia of preselected type, such as a predetermined color spectrum; preferably,…
System, method, and computer program product for providing feedback during formal verification
Granted: November 19, 2019
Patent Number:
10482206
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, at least one electronic design file and a set of inputs from a user, wherein the at least one electronic design file and set of inputs are associated with an electronic design. Embodiments may further include performing formal verification on at least a portion of the electronic design and determining, using a model checker, one or more conflicts associated…
Method and system for reconstructing virtual address from physical memory
Granted: November 19, 2019
Patent Number:
10482031
A method for retrieving a virtual address from a physical address accesses in a memory of a computing system, to which that virtual address was previously mapped to, may include: using a monitor to intercept transmissions to and from a memory of a computing system; using a processor: identifying in the intercepted transmissions page table address calls relating to mapping of a virtual address to a physical address; and retrieving the virtual address from the identified page table address…
Method and system for implementing high speed source synchronous clock alignment
Granted: November 12, 2019
Patent Number:
10476658
Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.
Layout placement mapping from schematic placement of circuit cells
Granted: November 12, 2019
Patent Number:
10474782
The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes…
System, method, and computer program product for floorplanning in an electronic circuit design
Granted: November 5, 2019
Patent Number:
10467371
The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying,…
Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design
Granted: November 5, 2019
Patent Number:
10467370
Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be…
Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design
Granted: November 5, 2019
Patent Number:
10467365
The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal (“cppr”) database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further…
Modeling of sequential circuit devices of multi-clock domain IC design for a transient vectorless power analysis
Granted: October 29, 2019
Patent Number:
10460055
A computer performing a transient vectorless power analysis of a multi-clock domain integrated circuit (IC) design may execute a scheduling cycle based on the dominant clock frequency and schedule events based on comparing instance clock frequencies with the dominant clock frequency. If the instance clock frequency matches the dominant clock frequency, the computer may schedule a single event per scheduling cycle for the sequential circuit devices driven by the respective instance…
Routing framework to resolve single-entry constraint violations for integrated circuit designs
Granted: October 29, 2019
Patent Number:
10460066
Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single…
Routing topology generation using spine-like tree structure
Granted: October 29, 2019
Patent Number:
10460065
Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system…
Partition-aware grid graph based hierarchical global routing
Granted: October 29, 2019
Patent Number:
10460064
Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid…
Integrated circuit routing based on enhanced topology
Granted: October 29, 2019
Patent Number:
10460063
Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing…
System and method for generating reduced standard delay format files for gate level simulation
Granted: October 29, 2019
Patent Number:
10460059
A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.
