Modeling of sequential circuit devices of multi-clock domain IC design for a transient vectorless power analysis
Granted: October 29, 2019
Patent Number:
10460055
A computer performing a transient vectorless power analysis of a multi-clock domain integrated circuit (IC) design may execute a scheduling cycle based on the dominant clock frequency and schedule events based on comparing instance clock frequencies with the dominant clock frequency. If the instance clock frequency matches the dominant clock frequency, the computer may schedule a single event per scheduling cycle for the sequential circuit devices driven by the respective instance…
Method, system, and computer program product for implementing routing aware placement for an electronic design
Granted: October 22, 2019
Patent Number:
10452807
Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted…
Generating a colored track pattern of non-uniform width from a sparse set of tracks
Granted: October 22, 2019
Patent Number:
10452806
Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various…
System and method for electronic design space tuning
Granted: October 22, 2019
Patent Number:
10452799
The present disclosure relates to a system and method for use with an electronic circuit design. The method may include providing, using at least one processor, an electronic design and modeling the electronic design to obtain a characteristic distribution associated with the electronic design, wherein modeling includes randomly varying one or more parameters associated with the electronic design. The method may further include identifying at least one key parameter from the modeled…
System, method, and computer program product for filtering one or more failures in a formal verification
Granted: October 22, 2019
Patent Number:
10452798
The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing formal verification of at least a portion of the electronic design having an original property. Embodiments may further include analyzing at least one output net bit associated with a check of the electronic design. Embodiments may also include generating a structural observability…
System and method for adaptively optimized refresh of memory
Granted: October 15, 2019
Patent Number:
10446215
A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational…
Interactive routing with poly vias
Granted: October 15, 2019
Patent Number:
10445459
The present embodiments are directed generally to techniques for providing an interactive environment that gives visual feedback and indicators to identify and/or encourage effective sharing of partially used drill sites, all inside a typical etch-edit environment. Such an interactive environment allows designers to effectively leverage and exploit new PCB manufacturing techniques that allow for multi-net use of a single drill hole.
Methods, systems, and articles of manufacture for implementing a physical design of an electronic design with DFM and design specification awareness
Granted: October 15, 2019
Patent Number:
10445457
Disclosed are techniques for implementing a physical design of an electronic design with design for manufacturing DFM and design specification awareness. These techniques identify one or more design specifications for generating a floorplan or a placement layout of an electronic design. Floorplanning or placement requirements are determined based in part or in whole upon pertinent electrical parasitics. The floorplan or the placement layout is generated at least by inserting a set of…
System and method for a smart configurable high performance interactive log file viewer
Granted: October 15, 2019
Patent Number:
10445290
A system, method, and computer program product for interactively viewing output log files in an electronic design automation framework. An interactive log file viewer may be configured to identify text objects (such as warnings and error messages) in log files, to render the text objects in a display according to a registered style, and to define responses triggered by user interface interaction with the text objects. Embodiments may read portions of the log files and use plug-ins to…
System and method for recommending integrated circuit placement and routing options
Granted: October 8, 2019
Patent Number:
10437954
The present disclosure relates to a system and method for electronic design recommendations. Embodiments may include receiving, using at least one processor, an electronic design. Embodiments may further include recognizing one or more circuits within the electronic circuit design. Embodiments may also include identifying one or more user-specific circuit performance preferences. Embodiments may further include generating a first set of one or more placement and routing topology…
System and method for use in physical design processes
Granted: October 8, 2019
Patent Number:
10437567
The present disclosure relates to a computer-implemented method for use in an electronic design environment. Embodiments may include defining, using at least one processor, a grammar object system including one or more of objects, elements, values and relationships. Embodiments may include generating a technology grammar binary representation, based upon, at least in part, the grammar object system and receiving a technology ASCII representation. Embodiments may further include parsing…
Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation
Granted: October 1, 2019
Patent Number:
10430536
An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common…
Method and system to transfer data between hardware emulator and host workstation
Granted: October 1, 2019
Patent Number:
10430215
An emulation system comprises a first computing device having a processor configured to generate a synchronization clock signal on receiving a data transfer request. The first computing device further comprises a first non-transitory machine-readable memory buffer storing machine readable binary data. The emulation system further comprises an emulator controller configured to receive the synchronization clock signal from the first computing device. The emulation system further comprises…
Electrostatic discharge cell placement using effective resistance
Granted: September 24, 2019
Patent Number:
10423754
In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to a design technique that can determine an optimal number and placement of ESD cells in a design for an IC. In embodiments, the technique includes determining an effective resistance criteria between a set of candidate ESD cells to the bumps/pads of the IC and finding a minimum set of ESD cells that covers all the bumps/pads. In embodiments, the technique is employed…
Method and apparatus for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes
Granted: September 24, 2019
Patent Number:
10423753
An approach is described for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes. According to some embodiments, the approach includes performance of parasitic analysis for the interface between nets and primitive/macro cell (blocks). Specifically, the approach includes performing parasitic analysis based on actual location information corresponding to overlap/connection between ports within blocks, external net connections…
Technology database independent components for integrated circuit package
Granted: September 24, 2019
Patent Number:
10423750
Disclosed herein are embodiments of systems, methods, and products providing technology database independent pcells to be seamlessly customized and implemented in a yet unknown IC package library. In particular, the technology database independent pcells may have a code to execute callback functions to retrieve the package library name of the parent cells hosting the pcells. Based upon the library name, the pcell code may access the technology files stored in the technology database of…
Reduced resource harmonic balance circuit simulations
Granted: September 24, 2019
Patent Number:
10423744
A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified,…
Constrained metric verification analysis of a system on chip
Granted: September 24, 2019
Patent Number:
10423741
A method including selecting multiple input parameters of a device configuration environment to perform multiple simulations on an electronic device defined by the device configuration environment is provided. The method with multiple values for the multiple input parameters and a value of an output parameter resulting from the multiple simulations, and extracting a distribution of output parameter values and a distribution of input parameter values from a database. The method also…
System, method, and computer program product for debugging in an electronic design file
Granted: September 17, 2019
Patent Number:
10417361
Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.
Power and scan resource reduction in integrated circuit designs having shift registers
Granted: September 17, 2019
Patent Number:
10417363
Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.
