Topology preserving schematic transformations for RF net editing
Granted: September 10, 2019
Patent Number:
10409948
The present embodiments relate to reconfiguration of a schematic. According to some aspects, embodiments relate to a method in which a schematic of a circuit is displayed on a graphical user interface of a computing device. The schematic can include a plurality of circuit objects, and at least one interconnect connecting the plurality of circuit objects to define a circuit connectivity. The method further includes defining a schematic reference point on the schematic. The method also…
Methods, systems, and computer program product for connectivity verification of electronic designs
Granted: September 10, 2019
Patent Number:
10409945
Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection…
Electronic design mapping process
Granted: September 10, 2019
Patent Number:
10409942
The present disclosure relates to a system and method for mapping an RTL vector file to an electronic design. Embodiments may include receiving, at one or more computing devices, an electronic design at an electronic design automation application and reading at least one gate-level netlist associated with the electronic design. Embodiments may also include preparing each gate object with different transformations so to match a register-transfer-level name and reading at least one vector…
Statistical sensitivity analyzer
Granted: September 10, 2019
Patent Number:
10409939
A method including evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration that improves a performance of the device is provided. The method includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal…
System, method, and computer program product for static and dynamic phase matching in an electronic circuit design
Granted: September 10, 2019
Patent Number:
10409934
The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, at an electronic design associated with one or more computing devices, a differential pair between a driver and a receiver. The method may further include identifying one or more segments associated with the differential pair and automatically solving, using the one or more computing devices, for a dynamic phase associated with the one or more segments.
Data array compaction in an emulation system
Granted: September 10, 2019
Patent Number:
10409624
Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes one or more processors configured to generate data in an emulation cycle. Each bit of the generated data is associated with a tag. The hardware emulator may include a compaction unit configured to receive the data generated by the one or more processors, and select one or more bits from total bits of the data based on valid tags associated with the bits of the data. The…
Command-oriented low power control method of high-bandwidth-memory system
Granted: September 10, 2019
Patent Number:
10409357
Embodiments of the invention provide a command-oriented method to lower power consumption of PHY during idle time periods. The idle time periods occur because HBM Commands have certain timing windows where there is no data transmission on DFI data signals between the memory controller and the PHY data slice. These windows may be utilized to power down the PHY data slice data path through DFI signal handshaking. In contrast to the conventional low power mode, this method provides an…
Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components
Granted: September 3, 2019
Patent Number:
10402532
Various techniques implement an electronic design with electrical analyzes with compensation circuit components. A power pin of a power net may be identified in an electronic design. The electronic design may be reduced into a reduced electronic design at least by applying one or more circuit reduction techniques to at least a portion of the electronic design. At least one load device of a plurality of load devices in the reduced electronic design may be transformed into a transformed…
Concurrent design process
Granted: September 3, 2019
Patent Number:
10404700
The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include storing a lock list at a client computing device, wherein the lock list includes objects associated with an electronic design that have been locked or unlocked. Embodiments may further include receiving a user input corresponding to a lock/unlock request associated with an object of the design, wherein the design is accessible by multiple users in…
Placement of cells in a multi-level routing tree
Granted: September 3, 2019
Patent Number:
10402533
Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first…
Method, system, and computer program product for implementing placement using row templates for an electronic design
Granted: September 3, 2019
Patent Number:
10402530
Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout…
Methods, systems, and articles of manufacture for implementing an electronic design with transistor level satisfiability models
Granted: September 3, 2019
Patent Number:
10402525
The described techniques implement an electronic design with transistor level satisfiability models by identifying a plurality of channel connected components of an electronic design for sensitization. These techniques further determine a set of transistor level satisfiability (SAT) models for the plurality of channel connected components of the electronic design and transform the plurality of channel connected components into a set of conjunctive normal form (CNF) formulae using at…
Region aware clustering
Granted: September 3, 2019
Patent Number:
10402522
Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each…
Register-transfer level design engineering change order strategy
Granted: August 27, 2019
Patent Number:
10395747
An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated,…
Methods, systems, and computer program products for implementing an electronic design using voltage-based electrical analyses and simulations with corrections
Granted: August 27, 2019
Patent Number:
10395000
Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of…
Methods and systems for schematic driven 2D chaining in an integrated circuit layout
Granted: August 27, 2019
Patent Number:
10394995
Disclosed herein are embodiments of systems, methods, and products that generate two dimensional chains of layout devices, by retrieving the schematic orientation of schematic devices in a symbolic view, and abutting the layout devices based on the schematic orientation such that the two dimensional chains of the layout devices maintain the schematic orientation. More specifically, EDA systems and methods disclosed herein may separate the layout devices into different sets, wherein each…
Method and system for reusing a refinement file in coverage grading
Granted: August 27, 2019
Patent Number:
10394699
A method for reuse of a refinement file in coverage grading, may include obtaining a refinement file that includes a listing of coverage entities of a first coverage model, for exclusion from a calculation of coverage grading of the first coverage model; obtaining mapping information to map a source path of each of the modules or instances of a module, that include one or more of said coverage entities in the first coverage model to a target path of each of said modules or instances of a…
Method and system to mitigate large power load steps due to intermittent execution in a computation system
Granted: August 20, 2019
Patent Number:
10386909
Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of…
Verifying results in simulation through simulation add-on to support visualization of selected memory contents in real time
Granted: August 20, 2019
Patent Number:
10387598
An exemplary bitmap file can be provided, which can include, for example, a map of a cell array structure of a memory(ies), a plurality of memory values superimposed on the cell array structure based on a simulated testing of the memory(ies). The memory values may be values being written to the memory(ies) while the memory(ies) is being tested. The memory values may be values in a test pattern(s) being used to test the memory(ies). Each cell in the cell array structure can have a…
Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit
Granted: August 20, 2019
Patent Number:
10387595
Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated…
