Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit
Granted: August 20, 2019
Patent Number:
10387595
Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated…
Method and system to mitigate large power load steps due to intermittent execution in a computation system
Granted: August 20, 2019
Patent Number:
10386909
Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of…
Systems and methods for modifying a balanced clock structure
Granted: August 13, 2019
Patent Number:
10380287
Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is…
System and method for estimating current in an electronic circuit design
Granted: August 13, 2019
Patent Number:
10380314
The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and identifying a partially routed net associated with the electronic design. Embodiments may further include generating a net graph for the partially routed net and selecting a wire associated with the partially routed net. Embodiments may also include determining a missing current needed to satisfy Kirchhoff's Current Law (“KCL”)…
System, method, and computer program product for analyzing formal constraint conflicts
Granted: August 13, 2019
Patent Number:
10380312
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying one or more assumptions associated with the electronic design that are mutually in conflict. Embodiments may further include grouping the one or more assumptions that are mutually in conflict into a conflicting group of assumptions and iteratively disabling at least one of the conflicting group of assumptions.…
Method for waveform based debugging for cover failures from formal verification
Granted: August 13, 2019
Patent Number:
10380301
The present disclosure relates to a method for waveform based debugging in a formal verification of an integrated circuit. The method may include receiving, using at least one processor, an electronic circuit design and partitioning a cone of influence for a cover property of the electronic circuit design into design logic and property logic. The method may further include applying an X-value to all inputs associated with the cone of influence and performing an X-simulation until a fixed…
Methods, systems, and articles of manufacture for X-behavior verification of an electronic design
Granted: August 13, 2019
Patent Number:
10380295
Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node.…
System, method, and computer program product for generating bidirectional real number models in an electronic design
Granted: August 13, 2019
Patent Number:
10380294
The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for…
Methods, systems, and computer program product for implementing physics aware model reduction for three-dimensional designs
Granted: August 13, 2019
Patent Number:
10380293
Disclosed are techniques for implementing physics aware model reduction for a design. These techniques identify a design model and generate a first set of solutions with a first discretization scheme and a plurality of inputs. A second discretization scheme may be generated at least by performing geometry simplification and re-discretization based in part or in whole on one or more distributions from the first set of solution. With the second discretization scheme, a second set of…
Systems and methods for finite difference time domain simulation of an electronic design
Granted: August 13, 2019
Patent Number:
10380292
The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (“FDTD”) simulator, a time-domain…
System and method for signal processing using sorting based filtering
Granted: August 13, 2019
Patent Number:
10379813
Embodiments may include receiving an input block of data having one or more rows wherein each row includes one or more elements. Embodiments may further include adjusting the input block of data to generate a two-dimensional sorted block of data and identifying at least one position within the two-dimensional sorted block of data that cannot contain a median value or a desired Nth sorted value. Embodiments may also include sorting the two-dimensional block of data along one or more…
Continuous time linear receiver that minimizes intersymbol interference due to pre-cursor distortion
Granted: July 30, 2019
Patent Number:
10367661
A circuit and method for reducing intersymbol interference due to pre-cursor distortion. A first set of circuit elements located along a first circuit path of a receiver device process an analog input signal of the receiver to form an equalized representation of the input signal. A second set of circuit elements are located along a second circuit path that has lower latency than the first circuit path. The second set of circuit elements form a scaled signal as one of the following: a…
Adaptive pattern filtering for clock and data recovery to minimize interaction with decision feedback equalization
Granted: July 16, 2019
Patent Number:
10355889
Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal.
Method and apparatus for codeword boundary detection for a scrambled reed solomon code bitstream
Granted: July 16, 2019
Patent Number:
10355818
The present embodiments relate to methods and apparatuses for detecting a codeword boundary and/or performing codeword error correction for a bitstream comprising scrambled Reed Solomon codewords. In accordance with some aspects, detecting a codeword boundary involves the use of the parity and symbols from a previous window to help in detecting a codeword boundary when the next input bit is received. In accordance with other aspects, parity symbols are more efficiently updated for each…
Systems and methods for clock tree generation with buffers and inverters
Granted: July 16, 2019
Patent Number:
10354040
Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.
Method, system, and computer program product for implementing legal placement with contextual awareness for an electronic design
Granted: July 16, 2019
Patent Number:
10354039
Disclosed are techniques for implementing legal placement with contextual awareness for an electronic design. These techniques identify one or more hierarchies from one or more groups or one or more instances located at these one or more hierarchies in a layout or floorplan. A plurality of instances including the one or more identified instances may be promoted to an honorary top hierarchy. A layout operation may then be performed on the one or more identified instances based in part or…
Methods, systems, and computer program product for implementing an electronic design by manipulating a hierarchical structure of the electronic design
Granted: July 16, 2019
Patent Number:
10354037
Disclosed are methods, systems, and articles of manufacture for manipulating a hierarchical structure of the electronic design. These techniques identify a set of layout components instantiated from a layout of an electronic design. This set of layout components may constitute, for example, a FigGroup. One or more schematic instances and corresponding schematic connectivity information may be identified from a schematic design of the electronic design, and the one or more schematic…
System and method for tuning a graphical highlight set to improve hierarchical layout editing
Granted: July 16, 2019
Patent Number:
10354034
The present embodiments relate generally to integrated circuit design, and more particularly to techniques that automatically and dynamically create or adjust a highlight set in a graphical user interface for allowing designers to edit layouts in a hierarchical design in a more productive manner. According to certain aspects, in dense designs and/or designs having complete or partial overlapping shapes, embodiments allow for highlighting more than one hierarchy level with tuned…
Fast settling bias circuit
Granted: July 9, 2019
Patent Number:
10345845
Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor…
Method and system for performing incremental post layout simulation with layout edits
Granted: July 9, 2019
Patent Number:
10346573
An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are…
