Simulation observability and control of all hardware and software components of a virtual platform model of an electronics system
Granted: July 2, 2019
Patent Number:
10339229
Aspects of the present invention describe a system and method for providing a single integrated simulation interface running in a single host operating system (OS) thread to observe and control multiple, disparate software and hardware components. Control mechanisms of the present invention provide access to each of the modeled components, including the hardware models, the embedded software components modeled on the bare-hardware elements, and the software applications, processes and…
Highly accurate defect identification and prioritization of fault locations
Granted: July 2, 2019
Patent Number:
10338137
A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.
Hybrid phase interpolator to correct integral non-linearity
Granted: June 25, 2019
Patent Number:
10333533
Aspects of the present disclosure include systems, methods, devices, and circuits for correcting integral non-linearity using a hybrid phase interpolator. Consistent with some embodiments, a circuit comprises a first and second phase interpolator mixer connected to an injection-locked ring. The first phase interpolator mixer provides a first injection signal to the injection-locked ring based on a clock signal, and the second phase interpolator mixer provides a second injection signal to…
Level shifter with sub-threshold voltage functionality
Granted: June 25, 2019
Patent Number:
10333502
Various embodiments provide for a level shifter with sub-threshold voltage functionality, which permits the level shifter to operate even when a voltage supply to the level shifter falls below a normal operational voltage range of one or more devices (e.g., transistors) within the level shifter. A level shift of an embodiment may operate when a voltage supply falls below a normal operational range in order to save power, which can be useful with respect to battery-operated devices, such…
Methods, systems, and computer program product for implementing virtual prototyping for electronic designs
Granted: June 25, 2019
Patent Number:
10331841
Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical…
System, method, and computer program product for capture and reuse in a debug workspace
Granted: June 25, 2019
Patent Number:
10331547
The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start…
SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores
Granted: June 25, 2019
Patent Number:
10331506
Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.
Virtual directory navigation and debugging across multiple test configurations in the same session
Granted: June 18, 2019
Patent Number:
10325048
An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select…
Failure boundary classification and corner creation for scaled-sigma sampling
Granted: June 18, 2019
Patent Number:
10325056
A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to…
Method and system for implementing custom inter-layer transitions for a multi-layer bus
Granted: June 18, 2019
Patent Number:
10325052
The present embodiments relate generally to techniques for creating and/or modifying multi-layer buses in an IC design. According to some more particular aspects, embodiments relate to techniques for allowing an IC designer to efficiently transition a multi-layer bus section made of N wires and M layers to another multi-layer bus section made of N wires and any other M? layers. In some embodiments, the user describes, programmatically, one or several custom transitions called a custom…
Debugging failures in X-propagation logic circuit simulation
Granted: June 18, 2019
Patent Number:
10325042
Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic…
Enhanced control system for flexible programmable logic and synchronization
Granted: June 18, 2019
Patent Number:
10324740
A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.
Customizable built-in self-test testplans for memory units
Granted: June 11, 2019
Patent Number:
10319459
An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed…
Balanced scaled-load clustering
Granted: June 11, 2019
Patent Number:
10318693
Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is…
Systems and methods for analyzing node impedance state
Granted: June 11, 2019
Patent Number:
10318682
Various embodiments provide for analyzing impedance states of a set of nodes in a circuit design and providing a set of reasons for those impedance states. The set of reasons can include a reason regarding why a particular node is reported as being in high-impedance (highz) state or in low-impedance (lowz) state, and the reason may be for a specific time point during transient analysis of the circuit design. Some embodiments are implemented within a debugging utility of an electronic…
Full-chip hierarchical inverse lithography
Granted: June 4, 2019
Patent Number:
10310372
According to certain aspects, the present embodiments relate to an inverse lithography technology (ILT) solution that provides masks with perfect symmetry and minimal complexity. A methodology according to the embodiments includes several steps and strictly maintains symmetry in each of these steps. In one step, lithographic model kernels are processed to enforce symmetry corresponding to an illumination source. In another step, an ideal grayscale mask for a target pattern is computed…
Method and system to mitigate large power load steps due to intermittent execution in a computation system
Granted: May 28, 2019
Patent Number:
10303230
Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of…
Frequency and phase measurement circuit
Granted: May 28, 2019
Patent Number:
10305498
Various embodiments provide for a circuit for measuring a frequency difference, a phase difference, or both of at least two clock signals (e.g., a reference clock signal and a feedback clock signal). In particular, various embodiments described herein may be used in a circuit design to convert an input phase of two clock signals to a frequency difference, which may be outputted in the form of a digital word. Additionally, various embodiments described herein may be used in a circuit…
Integrated circuit simulation with efficient memory usage
Granted: May 28, 2019
Patent Number:
10303828
A method for simulating an integrated circuit design is provided. The method includes executing a characterization tool over a first portion of a parameter space of a circuit design to form a netlist associated with the first portion of the parameter space. The method also includes forming a first sub-netlist from the netlist, selecting, for the first sub-netlist, a condition from at least one of a process, a voltage, or a temperature condition, and at least one parameter from the first…
System and method for memory control having address integrity protection for error-protected data words of memory transactions
Granted: May 28, 2019
Patent Number:
10303543
A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection…
