Systems and methods for memory protocol training
Granted: May 21, 2019
Patent Number:
10297311
Various embodiments provide for determining a delay of a data signal with respect to a data strobe signal within a memory system comprising a memory controller and a memory module. In particular, some embodiments adjust a phase between a data signal and a data strobe signal such that a data eye of the data signal arrives at a receiver latch of a memory module can be centered on a transition of the data strobe signal. By centering the data eye of the data signal with the transition of the…
System and method for visualization in an electronic circuit design
Granted: May 21, 2019
Patent Number:
10296703
The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in…
Method, system, and computer program product for implementing track patterns for electronic circuit designs
Granted: May 21, 2019
Patent Number:
10296695
Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to…
Method and system for generating validation tests
Granted: May 21, 2019
Patent Number:
10295596
A method for generating a validation test may include using a processor, identifying, in a scenario for validation testing, a plurality of actions that address a single resource in a conflicting manner; and automatically generating target code of the scenario that includes one or a plurality of resource management commands so as to prevent conflicting addressing of that resource by said plurality of actions.
Systems and methods for clustering pins for power
Granted: May 14, 2019
Patent Number:
10289792
Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.
Transform domain regression convolutional neural network for image segmentation
Granted: May 14, 2019
Patent Number:
10290107
Aspects of the present disclosure involve a transform domain regression convolutional neural network for image segmentation. Example embodiments include a system comprising a machine-readable storage medium storing instructions and computer-implemented methods for classifying one or more pixels in an image. The method may include analyzing the image to estimate one or more transform domain coefficients using a multi-layered function such as a convolutional neural network. The method may…
System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design
Granted: May 14, 2019
Patent Number:
10289798
The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design.…
Local cluster refinement
Granted: May 14, 2019
Patent Number:
10289797
Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of…
Routing tree topology generation
Granted: May 14, 2019
Patent Number:
10289795
Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may…
System and method to generate schematics from layout-fabrics with a common cross-fabric model
Granted: May 14, 2019
Patent Number:
10289793
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries…
Anchor-point based hierarchical electronic design process
Granted: May 14, 2019
Patent Number:
10289791
The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using a processor, an electronic design having a plurality of shapes associated therewith and displaying, at a graphical user interface, a first shape of the plurality of shapes. Embodiments may further include receiving a selection of an anchor point within the first shape, wherein the anchor point defines a fixed area associated with the first shape. Embodiments may also include…
System and method for suggesting components associated with an electronic design
Granted: May 14, 2019
Patent Number:
10289788
The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the…
System and method for managing configuration data associated with an electronic design
Granted: May 14, 2019
Patent Number:
10289783
The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing, using at least one processor, an electronic circuit design and generating a configuration associated with a portion of the electronic circuit design. Embodiments may further include associating a label with the configuration at a graphical user interface and applying the configuration to at least one of a design object, a sub-design, or the…
System and method for customizing key performance indicators in an electronic design
Granted: May 14, 2019
Patent Number:
10289782
The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include providing, using at least one processor, an electronic circuit design at a graphical user interface. Embodiments may further include associating one or more metrics with the electronic circuit design, wherein the one or more metrics include at least one of process metrics, design metrics, issues, library metrics, and custom metrics. Embodiments may further include…
Systems and methods for performing electromigration and voltage drop verification in electronic circuit designs
Granted: May 14, 2019
Patent Number:
10289780
Disclosed herein are systems and methods to perform electrical analysis of a circuit design to verify electrical behavior and performance of the circuit design in a two-step process. Initially, a simulator transient analysis is performed on circuit blocks of a circuit design to obtain a current through each device path in each circuit block, and using the current obtained the IR drop and EM problems are examined to get EM-IR drop analysis. Next, a simulator transient analysis is…
Systems and methods for assigning clock taps based on timing
Granted: May 14, 2019
Patent Number:
10289775
Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may…
Systems and methods for reuse of delay calculation in static timing analysis
Granted: May 14, 2019
Patent Number:
10289774
Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.
Parallel extraction of worst case corners
Granted: May 14, 2019
Patent Number:
10289764
Methods and systems are provided. In one aspect, a method for parallel extraction of worst case corners of a number of electronic design automation (EDA) simulations includes generating multiple initial EDA simulation results for a number of specifications of an integrated circuit based on a first algorithm. For each specification, a respective first set of input samples is generated based on a second algorithm using generated multiple initial simulation results. Using a third algorithm,…
Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory
Granted: May 7, 2019
Patent Number:
10282250
Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding…
Support for multiple user defined assertion checkers in a multi-FPGA prototyping system
Granted: May 7, 2019
Patent Number:
10282501
A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a…
