Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns
Granted: May 7, 2019
Patent Number:
10282505
Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques identify at least a layout or a portion thereof and determine one or more legal sets of routing tracks for the layout or the portion. One or more figure groups are identified or generated at a first virtual hierarchy, and the one or more first figure groups inherit respective portions of the one or more legal sets of…
Support for multiple user defined assertion checkers in a multi-FPGA prototyping system
Granted: May 7, 2019
Patent Number:
10282501
A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a…
Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory
Granted: May 7, 2019
Patent Number:
10282250
Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding…
Alias register file for supporting mixed width datapath in a configurable processor
Granted: May 7, 2019
Patent Number:
10282206
According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on…
Yield estimation for a post-layout circuit design
Granted: April 30, 2019
Patent Number:
10275555
Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further…
Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design
Granted: April 30, 2019
Patent Number:
10275554
A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining…
System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations
Granted: April 30, 2019
Patent Number:
10275306
A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking…
Converting real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environments
Granted: April 16, 2019
Patent Number:
10262088
A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design,…
Conversion of real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environments
Granted: April 16, 2019
Patent Number:
10262095
A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in…
Interactive platform to predict mismatch variation and contribution when adjusting component parameters
Granted: April 16, 2019
Patent Number:
10262092
A method for determining mismatch variation of circuit components in a circuit is provided. The method includes determining a mismatch contribution for a specification of an integrated circuit design and displaying a list of components in the circuit design sorted according to the mismatch contribution. The method also includes displaying an adjustable scale for a size of the component, modifying the circuit design according to with the size of the component adjusted according to a user…
Method and system for computerized debugging assertions
Granted: April 16, 2019
Patent Number:
10261887
A method for assertion debugging may include identifying in signals relating to an execution run of a code a segment of time for which an assertion has failed. The method may also include searching in the signals relating to that execution run, or in signals relating to another execution run of that code, to find one or a plurality of segments of time in which the signals are similar to the signals in the identified segment, for which the assertion was successful.
Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs
Granted: April 9, 2019
Patent Number:
10255403
A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged…
System and method for instance snapping
Granted: April 9, 2019
Patent Number:
10255402
Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to snap instances to a set of such tracks such that all pins/shapes in the instance result in valid locations. In some embodiments, the…
Reduced overhead for massive parallel processing
Granted: April 9, 2019
Patent Number:
10255394
A method for simulating an integrated circuit model is provided. The method includes receiving partition netlists of an integrated circuit in a partition scheduler and scheduling, by at least one computer, an execution of a computational thread associated with a first partition netlist. The method also includes preparing input data for a task and storing the input data set in an object storage. Also, the method includes executing, by the computer, the task in the computational thread.…
Integrated circuit simulation with data persistency for efficient memory usage
Granted: April 2, 2019
Patent Number:
10248747
A method for simulating an integrated circuit (IC) is provided. The method includes parsing an IC and loading the IC into memory and forming a table model including parameter values for at least one circuit component in the IC, the parameter values selected from a portion of a parameter space, storing a data value associated with the parsing of the IC and the table model in a database accessible through a cloud computing environment, the data value comprising a metadata associated with…
Method and apparatus for estimating ideal power of an integrated circuit design
Granted: April 2, 2019
Patent Number:
10248746
A method for determining power consumed by a circuit is described that includes identifying a redundant frame including one of a clock toggle or a data toggle that is not propagated to an output pin of the circuit and identifying a non-redundant frame comprising a clock toggle and a data toggle that are propagated to the output pin of the circuit. Further, the method includes determining an ideal power consumed by the circuit during the non-redundant frame and providing a feedback to the…
Integrated circuit simulation with variability analysis for efficient memory usage
Granted: April 2, 2019
Patent Number:
10248745
A method for simulating an integrated circuit design is provided. The method includes forming a partition of an IC netlist into blocks based on a performance value from at least a portion of a parameter space and forming a table with parameter values including multiple instances of at least one block of the partition. The computer-implemented method also includes analyzing a direct-current (DC) solution of at least one block by combining at least a first instance of a first block with a…
Optimizing a power grid for an integrated circuit
Granted: March 26, 2019
Patent Number:
10242145
The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and…
Optimizing core wrappers in an integrated circuit
Granted: March 19, 2019
Patent Number:
10234504
According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments,…
Exhaustive input vector stimuli for signal electromigration analysis
Granted: March 19, 2019
Patent Number:
10235482
A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components.…
