Exhaustive input vector stimuli for signal electromigration analysis
Granted: March 19, 2019
Patent Number:
10235482
A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components.…
Optimizing core wrappers in an integrated circuit
Granted: March 19, 2019
Patent Number:
10234504
According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments,…
Low-frequency periodic signal detector
Granted: March 5, 2019
Patent Number:
10225115
A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria…
System and method for tuning a graphical highlight set to improve hierarchical layout awareness and editing
Granted: March 5, 2019
Patent Number:
10223495
The present embodiments relate generally to integrated circuit design, and more particularly to techniques for providing enhanced visual information about a shape of interest in a hierarchical design. For example, embodiments relate to automatically and dynamically creating or adjust a highlight set in a graphical user interface for providing hierarchical information about shapes in a hierarchical design in a more productive manner, and possibly concurrently with other textual…
Spice model bin inheritance mechanism
Granted: March 5, 2019
Patent Number:
10223484
A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain…
Securing access to integrated circuit scan mode and data
Granted: March 5, 2019
Patent Number:
10222417
Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments…
Constraint validation process
Granted: February 26, 2019
Patent Number:
10216888
The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule…
Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis
Granted: February 26, 2019
Patent Number:
10216887
Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least…
Systems and methods for power efficient flop clustering
Granted: February 26, 2019
Patent Number:
10216880
Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a…
System and method for implementing and validating star routing for power connections at chip level
Granted: February 19, 2019
Patent Number:
10210301
A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by…
Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design
Granted: February 19, 2019
Patent Number:
10210299
Disclosed are methods, systems, and articles of manufacture for dynamically abstracting virtual hierarchies for an electronic design. These techniques identify at least a portion of a layout of an electronic design and a virtual hierarchy in the layout portion according to a value for a display stop level. A plurality of figure groups at one or more virtual hierarchies in the layout portion may also be identified in the layout portion. These techniques select a plurality of layout…
Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques
Granted: February 12, 2019
Patent Number:
10204201
Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately…
Method and system for implementing data reduction for waveform data
Granted: February 12, 2019
Patent Number:
10204187
An improved approach is provided to generate and display waveform data, where data reduction is intelligently applied to create filtered waveform data. By reducing the quantity of the waveform data in an intelligent manner, this permits the waveform display tool to process the waveforms quickly enough for interactive usage, while still retaining sufficient data fidelity for accurate data analysis and waveform visualization.
Method, system, and computer program product for implementing electronic designs with automatically generated power intent
Granted: February 12, 2019
Patent Number:
10204180
Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the…
Methods and systems for implementing high bandwidth memory command address bus training
Granted: February 12, 2019
Patent Number:
10203875
A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA…
Clock cell library selection
Granted: February 5, 2019
Patent Number:
10198551
Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell…
System and method for profiling during an electronic design simulation
Granted: February 5, 2019
Patent Number:
10198540
The present disclosure relates to a computer-implemented method for electronic design simulation using a profiler. The method may include simulating, using a computing device, an electronic design associated with a programming language. The method may further include recording a first time corresponding to a first user-defined point in the simulation. The method may also include recording a second time corresponding to a second user-defined point in the simulation. The method may further…
Systems and methods for dynamic RTL monitors in emulation systems
Granted: February 5, 2019
Patent Number:
10198539
Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator…
Relocate targets to different domains in an emulator
Granted: February 5, 2019
Patent Number:
10198538
The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by…
Method and system for implementing efficient trim data representation for an electronic design
Granted: January 29, 2019
Patent Number:
10192018
An improved approach is described to implement trim data representation for an electronic design. Instead of maintaining a gap shape object for every gap in the layout, existing objects adjacent to the gap location are configured to include attributes of the gap shape. The properties of the gap shape can then be derived from the adjacent objects.
