Generating and inserting metal and metal etch shapes in a layout to correct design rule errors
Granted: January 29, 2019
Patent Number:
10192021
Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and…
Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design
Granted: January 29, 2019
Patent Number:
10192020
Disclosed are methods, systems, and articles of manufacture for implementing dynamic maneuvers within virtual hierarchies of an electronic design. These techniques identify or generate a plurality of figure groups at one or more virtual hierarchies in a layout portion and receive a request to descend into or ascend from a figure group at a virtual hierarchy of the one or more virtual hierarchies. In response to the received request, these techniques update a layout view into an updated…
Method and system for implementing efficient trim data representation for an electronic design
Granted: January 29, 2019
Patent Number:
10192018
An improved approach is described to implement trim data representation for an electronic design. Instead of maintaining a gap shape object for every gap in the layout, existing objects adjacent to the gap location are configured to include attributes of the gap shape. The properties of the gap shape can then be derived from the adjacent objects.
Test logic at register transfer level in an integrated circuit design
Granted: January 29, 2019
Patent Number:
10192013
Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage,…
Methods and devices for extraction of MEMS structures from a MEMS layout
Granted: January 22, 2019
Patent Number:
10185797
Electronic design automation systems and methods for extracting Microelectromechanical systems (MEMS) objects from a manufacturing MEMS layout are described for MEMS layouts directed to MEMS devices including mass and spring objects. Pattern recognition is used on a MEMS layer of the MEMS layout to identify beams and supports. The identified beams and supports are then used to derive a set of intermediate MEMS objects. The intermediate MEMS objects are used to derive a set of output…
Systems and methods for statistical static timing analysis
Granted: January 22, 2019
Patent Number:
10185795
Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can…
Scheduling parallel processing of multiple partitions for signal electromigration analysis
Granted: January 15, 2019
Patent Number:
10181000
A method for determining an electromigration effect in an integrated circuit model with multiple parallel processors is provided. The method includes receiving, in a partition scheduler, a circuit netlist divided into smaller partition netlists in a partition scheduler and scheduling a computational thread including tasks associated with a first partition netlist, and verifying that at least one task in the first computational thread has been executed by at least one computer selected…
System and method performing scan chain diagnosis of an electronic design
Granted: January 15, 2019
Patent Number:
10180457
The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to…
System and method for data transmission
Granted: January 8, 2019
Patent Number:
10177940
The present disclosure relates to an apparatus for use in a transition-minimized differential signaling link (“TMDS”) receiver. The apparatus may include an integrated circuit electrically connected with a voltage supply. The integrated circuit may include a first transistor, a second transistor, and a resistor arranged in a cascaded configuration along a termination path. The first transistor may include calibration code control configured to adjust an output impedence.
System and method for optimizing a parts list associated with an electronic design
Granted: January 8, 2019
Patent Number:
10178080
The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include providing an initial electronic circuit design and receiving an initial parts list configured to include at least one of logical parts and physical parts associated with the initial electronic circuit design. Embodiments may further include providing authorization to at least one user to edit the initial parts list via a graphical user interface, wherein the at least…
System and method for placing components in an electronic circuit design
Granted: January 8, 2019
Patent Number:
10176288
The present disclosure relates to a system and method for modeling the placement of components in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design at a graphical user interface (GUI) and a selection for a component to be placed within the electronic circuit design. Embodiments may also include detecting a change in the position of the selected component to determine when the selected component is moved into a…
System, method, and computer program product for oscillating loop detection in formal verification
Granted: January 8, 2019
Patent Number:
10176286
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design having a plurality of loops and removing a section of each of the plurality of loops. The method may further include obtaining an input/output net for each of the plurality of loops and generating a copy of at least a portion of the electronic design. The method may include connecting all inputs except a loop cut…
System, method, and computer program product for property violation comprehension
Granted: January 8, 2019
Patent Number:
10176285
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying at least one property violation associated with the electronic design. Embodiments may further include generating a sensitivity path from an input to the at least one property violation. Embodiments may also include analyzing the electronic design to identify one or more of a portion of the electronic design…
Determining an optimal global quantum for an event-driven simulation
Granted: January 8, 2019
Patent Number:
10176276
An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against…
Methods, systems, and computer program product for a PCI implementation handling multiple packets
Granted: January 8, 2019
Patent Number:
10176126
Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and…
Cache coherency process
Granted: January 8, 2019
Patent Number:
10176100
The present disclosure relates to a system and method for maintaining coherency in the memory subsystem of an electronic system modeled in dual abstractions. Embodiments may include providing a mixed abstraction simulation model including an abstract portion and a detailed portion, wherein the detailed portion includes a cache coherent interconnect and a coherency proxy. Embodiments may further include establishing, within the detailed portion, communication between an extended smart…
Debugging process
Granted: January 8, 2019
Patent Number:
10176078
The present disclosure relates to a system and method for capturing log messages in a post-processing debugging environment. Embodiments may include receiving a processor model associated with an electronic design and generating, using one or more processors and the processor model, a complete view of the state of the memory. Embodiments may further include writing, using one or more processors and the processor model, a log message whenever a designated message logging function is…
Systems and methods for correcting for pre-cursor and post-cursor intersymbol interference in a data signal
Granted: January 1, 2019
Patent Number:
10171270
Various embodiments provide for correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in a data signal received over a channel. More particularly, some embodiments correct pre-cursor ISI and post-cursor ISI using decision feedback equalization (DFE).
Timing context generation with multi-instance blocks for hierarchical analysis
Granted: January 1, 2019
Patent Number:
10169501
Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing…
System and method for a low-power processing architecture
Granted: December 25, 2018
Patent Number:
10162632
The present disclosure relates to a system and method for use in a digital signal processing environment. Embodiments may include a programmable processor configured to execute an instruction set that includes multiply instructions and/or multiply-accumulate instructions that generate a result in carry-save format or redundant binary format. The instruction set may be executed at a single instruction, multiple data (SIMD) level.
