Methods and devices for charge pump level translation in high-speed memory drivers
Granted: December 25, 2018
Patent Number:
10164524
Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two…
System and method for performing out of order name resolution in an electronic design
Granted: December 25, 2018
Patent Number:
10162920
The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include…
Method and system for implementing selective transformation for low power verification
Granted: December 25, 2018
Patent Number:
10162917
Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.
System and method for a low-power processing architecture
Granted: December 25, 2018
Patent Number:
10162632
The present disclosure relates to a system and method for use in a digital signal processing environment. Embodiments may include a programmable processor configured to execute an instruction set that includes multiply instructions and/or multiply-accumulate instructions that generate a result in carry-save format or redundant binary format. The instruction set may be executed at a single instruction, multiple data (SIMD) level.
Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode
Granted: December 25, 2018
Patent Number:
10162522
Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic,…
Transconductor circuit for a fourth order PLL
Granted: December 11, 2018
Patent Number:
10153774
A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal.…
Method and system for synchronizing transaction streams of a partial sequence of transactions through master-slave interfaces
Granted: December 4, 2018
Patent Number:
10146714
A method for synchronizing transactions between components of a system on chip includes monitoring a partial sequence of transactions that use AXI communication protocol for a stream of address calls and a streams of transfer batches. For each of the address calls and transfer batches identified by the same unique identifier, extracting an anticipated an anticipated number of transfers per batch from each of the address calls of the stream of address calls, and recursively, comparing the…
Representing a routing strip in an integrated circuit design using a digit pattern
Granted: November 27, 2018
Patent Number:
10140410
Embodiments disclosed herein provide techniques for representing a routing strip in an integrated circuit design using a digit pattern. According to certain aspects, the techniques include methods to display overlapped routing strips of an integrated circuit design when there are ten or more metal layers in the integrated circuit design. According to additional or alternative aspects, the techniques include methods to generate a texture pattern for displaying routing strips in which…
Source code annotation for a system on chip
Granted: November 27, 2018
Patent Number:
10140202
A method including receiving source code for controlling a system on a chip and correlating a datum and an instruction in the source code with a first node is provided. The method includes associating the first node with a resource used by the datum and the instruction, based on a model for the system on a chip, illustrating a link between the first node and a second node, indicative of a data dependency in the source code between the first node and the second node, and evaluating a…
Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs
Granted: November 20, 2018
Patent Number:
10133842
Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active…
Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs
Granted: November 20, 2018
Patent Number:
10133841
Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon…
Method and apparatus for converting real number modeling to synthesizable register-transfer level emulation in digital mixed signal environments
Granted: November 20, 2018
Patent Number:
10133837
A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the…
Systems and methods for on-the-fly temperature and leakage power estimation in electronic circuit designs
Granted: November 20, 2018
Patent Number:
10133836
A method for on-the-fly determination of leakage power and temperature of an electronic circuit design is provided. The method includes calculating a dynamic power of the electronic circuit design. The method also includes calculating a total power consumption of the electronic circuit design. The method further includes averaging the total power consumption to obtain an average total power, determining a temperature of the electronic circuit design based on the average total power, and…
System and method for computationally optimized characterization of complex logic cells
Granted: November 20, 2018
Patent Number:
10133835
A system and method are provided for reducing processing time in characterizing a programmably implemented cell. The cell is decomposed into a plurality of channel connected component portions (CCC's), each including a local output node and at least one switching device establishing a conduction channel within a channel path extending from the local output node to a power plane of the cell. A component characteristic function is generated for each CCC, which logically sums a locus of…
Seamless interface for hardware and software data transfer
Granted: November 20, 2018
Patent Number:
10133683
An interface, a method, and a system are provided. In one or more aspects, the interface is for data transfer between simulation software and a hardware emulator associated with an integrated circuit design and includes a data producer to push a number of elements. A data element includes variable bits of data and variable bits of control information. A first-in-first-out (FIFO) receives the elements pushed by the data producer and stores pushed elements. A data consumer requests the…
Recording and playback of trace and video log data for programs
Granted: November 20, 2018
Patent Number:
10133653
Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the…
Low supply current mirror
Granted: November 20, 2018
Patent Number:
10133292
Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.
Code coverage mapping
Granted: November 20, 2018
Patent Number:
10132862
Methods and systems for code coverage mapping are provided. In one aspect, a method for code coverage mapping includes generating, by a user application executable by a computing device, a source-code handle corresponding to a transaction code. The source-code handle is communicated through an interface to a server emulating a design-under-test (DUT). Writing a value of the source-code handle to a signal in the DUT is facilitated to mark start of execution, by the user application, of…
Coupled inverter with auto-calibration
Granted: November 13, 2018
Patent Number:
10128965
A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage.…
System and method for hierarchical library searching
Granted: November 6, 2018
Patent Number:
10120968
The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined…
