System and method for hierarchical library searching
Granted: November 6, 2018
Patent Number:
10120968
The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined…
Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic
Granted: October 30, 2018
Patent Number:
10114920
A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby,…
Method and system to accelerate visualization of waveform data
Granted: October 30, 2018
Patent Number:
10114916
An improved approach is provided to provide fast access to waveform visualizations for electronic designs. Data reduction is performed on the waveform data, where the quantity of the waveform data is reduced in an intelligent manner, such that the reduced waveform data still retains sufficient data fidelity for accurate data analysis and waveform visualization. The reduced data can then be displayed in an accelerated manner. From the display of the reduced data, this allows the user to…
System and method for monitoring address traffic in an electronic design
Granted: October 30, 2018
Patent Number:
10114912
The present disclosure relates to a computer-implemented method for electronic design simulation is provided. Embodiments may include providing, using one or more processors, an electronic design configured to generate one or more address sequences. Embodiments may also include applying an address noise monitor to the electronic design, wherein the address noise monitor is configured to determine address noise data, wherein the address noise data includes a measure of one or more…
System and method for automated testing of user interface software for visual responsiveness
Granted: October 30, 2018
Patent Number:
10114733
A benchmark test system captures and records root, or input, behavior from a user input device as one or more time-displaced samples of input. The system also separately captures and records the canvas, or visual, behavior of a user interface in response to the captured input as a series of time-displaced image frames. The image frames are analyzed for visual prompts occurring responsive to the input, and parameters of the image frames are determined. A parametric difference between…
Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design
Granted: October 23, 2018
Patent Number:
10108767
Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock…
Method and system for performing regression session on a device under test
Granted: October 23, 2018
Patent Number:
10108514
A method for performing a regression session when testing a device under test (DUT), may include a. obtaining a coverage model of the DUT, and a verification session input file (VSIF) relating to a plurality of tests to be run on the DUT, the VSIF including an initial number of runs associated with each of the tests of the plurality of tests; b. performing a first iteration of the regression session in which each of the tests of the plurality of tests is run the initial number of runs…
System and method for constructing spanning trees
Granted: October 16, 2018
Patent Number:
10102328
The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with…
Memory built-in self-test logic in an integrated circuit design
Granted: October 9, 2018
Patent Number:
10095822
In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the…
Systems and methods for symmetric H-tree construction with complicated routing blockages
Granted: October 9, 2018
Patent Number:
10095824
Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such…
Transistor level low power verification for mixed signal circuit design
Granted: October 9, 2018
Patent Number:
10095821
Electronic design automation systems, methods, and computer readable media are presented for the generation of power-related connectivity data by an analog simulator (for example, by propagating the power supply data and/or ground data through the circuit components of the analog design schematic). In some embodiments, the verification module determines consistency between different versions of power-related connectivity data, such as: (i) power-related connectivity data from the analog…
Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design
Granted: October 9, 2018
Patent Number:
10094875
Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A…
Method and apparatus for design rules driven interactive violation display
Granted: September 18, 2018
Patent Number:
10078723
An approach is described for implementing a GUI that provides a user interface for reviewing and correcting design rule violations within a CAD program. According to some embodiments, a user may enter a serial review process which may utilize contextual information to determine where to start that review process. Further, the serial review process may enable the user to review rule violations in an individual manner for a respective object. Furthermore, a dynamic directional violation…
Data propagation analysis for debugging a circuit design
Granted: September 18, 2018
Patent Number:
10078714
A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of…
Methods, systems, and computer program product for implementing synchronous clones for an electronic design
Granted: September 11, 2018
Patent Number:
10073942
Disclosed are methods, systems, and articles of manufacture for implementing clones for an electronic design. These methods and systems identify a schematic design of an electronic design and a set of cloning rules, configurations, or settings for implementing clones for the electronic design. These methods and systems then generate a plurality of synchronous clones in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings,…
Systems and methods for statistical static timing analysis
Granted: September 11, 2018
Patent Number:
10073934
Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is…
Data compression engine for I/O processing subsystem
Granted: September 11, 2018
Patent Number:
10073795
In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation and returns test results and trace data. Channels of multiple buffers and associated processors implement the test operations. Compression units on each channel may compress the test and trace data to facilitate returning the results to the host device. Multiple channels may be used to compress data in parallel, thereby improving throughput.
Method and apparatus for high bandwidth memory read and write data path training
Granted: September 4, 2018
Patent Number:
10067689
According to certain general aspects, the present embodiments relate to methods and apparatuses for performing read and write data path training in HBMs. In accordance with some aspects, embodiments configure HBM mode registers for read and write data path training using an IEEE 1500 interface is simpler than the traditional scenario. In accordance with other aspects, the logic for performing read and write data path training is independent from normal memory access functionality in the…
Method for preventing mis-equalizations in decision feedback equalizer based receivers for low loss channels
Granted: September 4, 2018
Patent Number:
10069656
Systems and methods disclosed herein provide for preventing the mis-equalization of signals transmitted over short transmission channels. Embodiments of the systems and methods provide for a receiver including a digital receiver equalization circuit that selectively provides a correction signal to a DFE tap weight based on the value of the current DFE tap weight as well as the logical values of the in-phase and error data samples associated with received signal.
System and method for efficient device testing and validation of fast transients
Granted: September 4, 2018
Patent Number:
10068044
The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced…
