Method and apparatus for automatic diagnosis of mis-compares
Granted: August 28, 2018
Patent Number:
10060976
Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation (“ATPG”) generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.
Methods, systems, and computer program product for implementing a floorplan with virtual hierarchies and figure groups for an electronic design
Granted: August 21, 2018
Patent Number:
10055529
Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At…
Methods, systems, and computer program product for implementing engineering change orders with figure groups and virtual hierarchies
Granted: August 21, 2018
Patent Number:
10055528
Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the…
Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns
Granted: August 14, 2018
Patent Number:
10049175
Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a…
System and method for adaptively optimized recomposition of parts list for fabrication of electronic circuit product
Granted: August 7, 2018
Patent Number:
10043222
A system and method are provided for adaptively optimized recomposition of a parts list for fabrication of an electronic circuit product. A parts list acquisition portion forms a parts list containing a plurality of constituent parts entries read from one or more predetermined sources. The parts entries are respectively identified in the parts list by different corresponding part identifiers. An optimization unit coupled to the parts list acquisition unit comparatively determines mutual…
Hierarchical timing analysis for multi-instance blocks
Granted: July 31, 2018
Patent Number:
10037394
Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static…
System and method for memory control having self writeback of data stored in memory with correctable error
Granted: July 31, 2018
Patent Number:
10037246
A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data…
System, method, and computer program product for analyzing X-propagation failures in formal verification
Granted: July 24, 2018
Patent Number:
10031990
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. The method may further include identifying a plurality of X sources associated with the verification environment and modifying the plurality of X sources based upon, at least in part, the symbolic constant. The…
Systems and methods for congestion and routability aware detailed placement
Granted: July 24, 2018
Patent Number:
10031994
Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a…
System, method, and computer program product for testbench coverage
Granted: July 24, 2018
Patent Number:
10031991
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test (“DUT”) and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and…
System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based technique
Granted: July 24, 2018
Patent Number:
10031986
The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each…
Multi-layer incremental toolbar configuration system
Granted: July 17, 2018
Patent Number:
10025467
A system, method, and computer program product for automatically managing control configurations in an application graphical user interface (GUI). Interface element specifications may be configured via a customized overlay file corresponding to at least one party having influence over the application controlled by the GUI, such as an application vendor, a user group, and an individual user. The overlay file is created and saved via an interface manager GUI that allows new interface…
Method and system for efficient block synchronization scheme on a scrambled cyclic code bit stream
Granted: July 10, 2018
Patent Number:
10020824
An improved approach is provided to identifying the boundary of data encoded using additive cyclic codes. In some embodiment, the process includes determining a first calculated parity of a first bit stream window, and, second, one or more updates to the calculated parity of the bit stream window to determine the parity of the next bit stream window, where after each update to the calculated parity, the calculated parity is compared with the target parity, and matching the calculated…
Method and system for generalized next-state-directed constrained random simulation
Granted: June 26, 2018
Patent Number:
10007746
A system and method for generalized next-state-directed constrained random simulation may include obtaining an initial state for a finite state machine (FSM) constrained by a first Boolean random circuit; and unrolling the FSM, wherein each step of steps of the unrolling, except for a final step, is constrained by the first Boolean random circuit that defines a set of generalized cycles, and wherein the final step is constrained by a second Boolean random circuit.
Automated method identifying physical memories within a core or macro integrated circuit design
Granted: June 26, 2018
Patent Number:
10007489
A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the…
Method of adaptively controlling a low frequency equalizer
Granted: June 12, 2018
Patent Number:
9998303
A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal…
LevelShifter-less output buffer with hybrid driver for high speed and low supply memory applications
Granted: June 12, 2018
Patent Number:
9997214
Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.
Method and apparatus for placement and routing of analog components
Granted: June 5, 2018
Patent Number:
9990461
A method for placing and routing devices in a circuit layout is provided. The method includes determining devices to be placed in a circuit layout and a relative position of two devices in the circuit layout. In some embodiments, the method includes pre-routing channels in the circuit layout, determining routing trunk information from the pre-routed channels, and placing the two devices in the circuit layout based on the routing trunk information. Further, the method includes forming a…
Routing process including dynamically changing pad sizes
Granted: June 5, 2018
Patent Number:
9990456
The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part,…
Controller, system, and method for re-establishment of common mode in a transmission driver
Granted: May 29, 2018
Patent Number:
9985665
A method, control apparatus, and system for re-establishing a common mode in a transmitter involve switching a driver circuit of the transmitter to a quick charge or quick discharge mode based on an output value of the transmitter. When the output later exceeds a programmable common mode voltage, the driver circuit is switched to a classical margining mode to bring the output back towards the targeted common mode voltage. The modes are switched by adjusting the number of activated…
